 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DS26518 8-Port T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION The DS26518 is a single-chip 8-port framer and line interface unit (LIU) combination for T1, E1, and J1 applications. Each port is independently configurable, supporting both long-haul and short-haul lines. The 8-port SCT is software compatible with the DS26519 and nearly software compatible with the DS26528 and its derivatives. FEATURES Eight Complete T1, E1, or J1 Long-Haul/ Short-Haul Transceivers (LIU Plus Framer) Independent T1, E1, or J1 Selections for Each Transceiver Fully Internal Impedance Match, No External Resistor Software-Selectable Transmit- and ReceiveSide Termination for 100 T1 Twisted Pair, 110 J1 Twisted Pair, 120 E1 Twisted Pair, and 75 E1 Coaxial Applications Hitless Protection Switching Crystal-Less Jitter Attenuators Can Be Selected for Transmit or Receive Path; Jitter Attenuator Meets ETS CTR 12/13, ITU-T G.736, G.742, G.823, and AT&T Pub 62411 External Master Clock Can Be Multiple of 2.048MHz or 1.544MHz for T1/J1 or E1 Operation; This Clock is Internally Adapted for T1 or E1 Usage in the Host Mode Receive-Signal Level Indication from -2.5dB to -36dB in T1 Mode and -2.5dB to -44dB in E1 Mode in Approximate 2.5dB Increments Transmit Open- and Short-Circuit Detection LIU LOS in Accordance with G.775, ETS 300 233, and T1.231 Transmit Synchronizer Flexible Signaling Extraction and Insertion Using Either the System Interface or Microprocessor Port Alarm Detection and Insertion T1 Framing Formats of D4, SLC-96, and ESF J1 Support E1 G.704 and CRC-4 Multiframe T1-to-E1 Conversion Features Continued in Section 2. APPLICATIONS Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment FUNCTIONAL DIAGRAM DS26518 T1/E1/J1 NETWORK T1/J1/E1 Transceiver x8 BACKPLANE TDM ORDERING INFORMATION PART DS26518G DS26518G+ DS26518GN DS26518GN+ TEMP RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C PIN-PACKAGE 256 TE-CSBGA 256 TE-CSBGA 256 TE-CSBGA 256 TE-CSBGA + Denotes lead-free/RoHS compliant device. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 286 REV: 022007 DS26518 8-Port T1/E1/J1 Transceiver TABLE OF CONTENTS 1. 2. DETAILED DESCRIPTION.................................................................................................9 FEATURE HIGHLIGHTS ..................................................................................................10 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 GENERAL ......................................................................................................................................10 LINE INTERFACE ............................................................................................................................10 CLOCK SYNTHESIZERS ..................................................................................................................10 JITTER ATTENUATOR .....................................................................................................................10 FRAMER/FORMATTER ....................................................................................................................11 SYSTEM INTERFACE ......................................................................................................................11 HDCL CONTROLLERS ...................................................................................................................12 TEST AND DIAGNOSTICS ................................................................................................................12 MICROCONTROLLER PARALLEL PORT.............................................................................................12 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ............................................................12 3. 4. 5. 6. 7. 8. 8.1 APPLICATIONS ...............................................................................................................13 SPECIFICATIONS COMPLIANCE ...................................................................................14 ACRONYMS AND GLOSSARY .......................................................................................16 MAJOR OPERATING MODES.........................................................................................17 BLOCK DIAGRAMS.........................................................................................................18 PIN DESCRIPTIONS ........................................................................................................20 PIN FUNCTIONAL DESCRIPTION......................................................................................................20 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 FUNCTIONAL DESCRIPTION .........................................................................................28 PROCESSOR INTERFACE................................................................................................................28 SPI Serial Port Mode............................................................................................................................ 28 SPI Functional Timing Diagrams ......................................................................................................... 28 Backplane Clock Generation ............................................................................................................... 31 CLKO Output Clock Generation........................................................................................................... 32 9.1.1 9.1.2 9.2.1 9.2.2 CLOCK STRUCTURE.......................................................................................................................31 RESETS AND POWER-DOWN MODES..............................................................................................33 INITIALIZATION AND CONFIGURATION..............................................................................................34 Example Device Initialization and Sequence ....................................................................................... 34 9.4.1 GLOBAL RESOURCES ....................................................................................................................34 PER-PORT RESOURCES ................................................................................................................34 DEVICE INTERRUPTS .....................................................................................................................34 SYSTEM BACKPLANE INTERFACE ...................................................................................................36 Elastic Stores ....................................................................................................................................... 36 IBO Multiplexing ................................................................................................................................... 39 H.100 (CT Bus) Compatibility .............................................................................................................. 45 Transmit and Receive Channel Blocking Registers............................................................................. 47 Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 47 Receive Fractional Support (Gapped Clock Mode) ............................................................................. 47 T1 Framing........................................................................................................................................... 48 E1 Framing........................................................................................................................................... 51 T1 Transmit Synchronizer .................................................................................................................... 53 Signaling .............................................................................................................................................. 54 T1 Data Link......................................................................................................................................... 59 E1 Data Link......................................................................................................................................... 61 Maintenance and Alarms ..................................................................................................................... 62 2 of 286 9.8.1 9.8.2 9.8.3 9.8.4 9.8.5 9.8.6 9.9 FRAMERS......................................................................................................................................48 9.9.1 9.9.2 9.9.3 9.9.4 9.9.5 9.9.6 9.9.7 DS26518 8-Port T1/E1/J1 Transceiver 9.9.8 9.9.9 9.9.10 9.9.11 9.9.12 9.9.13 9.9.14 9.9.15 9.9.16 9.9.17 Alarms .................................................................................................................................................. 65 Error Count Registers .......................................................................................................................... 67 DS0 Monitoring Function...................................................................................................................... 69 Transmit Per-Channel Idle Code Generation ...................................................................................... 70 Receive Per-Channel Idle Code Insertion............................................................................................ 70 Per-Channel Loopback ........................................................................................................................ 70 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 70 T1 Programmable In-Band Loop Code Generator............................................................................... 71 T1 Programmable In-Band Loop Code Detection................................................................................ 72 Framer Payload Loopbacks ................................................................................................................. 73 9.10 9.10.1 9.10.2 HDLC CONTROLLERS ................................................................................................................74 Receive HDLC Controller..................................................................................................................... 74 Transmit HDLC Controller.................................................................................................................... 77 9.11 9.12 9.12.1 9.12.2 9.12.3 9.12.4 9.12.5 9.12.6 POWER-SUPPLY DECOUPLING....................................................................................................79 LINE INTERFACE UNITS (LIUS)....................................................................................................80 LIU Operation....................................................................................................................................... 82 Transmitter ........................................................................................................................................... 83 Receiver ............................................................................................................................................... 86 Hitless Protection Switching (HPS)...................................................................................................... 90 Jitter Attenuator.................................................................................................................................... 91 LIU Loopbacks ..................................................................................................................................... 92 9.13 9.13.1 9.13.2 BIT ERROR-RATE TEST FUNCTION (BERT) .................................................................................95 BERT Repetitive Pattern Set ............................................................................................................... 96 BERT Error Counter............................................................................................................................. 96 10. DEVICE REGISTERS .......................................................................................................97 REGISTER LISTINGS ...................................................................................................................97 Global Register List.............................................................................................................................. 98 Framer Register List............................................................................................................................. 99 LIU and BERT Register List............................................................................................................... 106 10.1.1 10.1.2 10.1.3 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 REGISTER BIT MAPS ................................................................................................................107 Global Register Bit Map ..................................................................................................................... 107 Framer Register Bit Map .................................................................................................................... 108 LIU Register Bit Map .......................................................................................................................... 117 BERT Register Bit Map ...................................................................................................................... 118 10.3 10.4 10.4.1 10.4.2 GLOBAL REGISTER DEFINITIONS...............................................................................................119 FRAMER REGISTER DESCRIPTIONS...........................................................................................133 Receive Register Descriptions........................................................................................................... 133 Transmit Register Descriptions.......................................................................................................... 191 10.5 10.6 LIU REGISTER DEFINITIONS .....................................................................................................227 BERT REGISTER DEFINITIONS .................................................................................................237 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................245 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................250 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................255 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................259 THERMAL CHARACTERISTICS....................................................................................................265 LINE INTERFACE CHARACTERISTICS..........................................................................................265 MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................266 SPI Bus Mode .................................................................................................................................... 266 11. FUNCTIONAL TIMING ...................................................................................................245 11.1 11.2 11.3 11.4 12. OPERATING PARAMETERS.........................................................................................264 12.1 12.2 13. AC TIMING CHARACTERISTICS ..................................................................................266 13.1.1 13.1 13.2 JTAG INTERFACE TIMING.........................................................................................................277 3 of 286 14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................278 DS26518 8-Port T1/E1/J1 Transceiver 14.1 TAP CONTROLLER STATE MACHINE .........................................................................................279 Test-Logic-Reset................................................................................................................................ 279 Run-Test-Idle ..................................................................................................................................... 279 Select-DR-Scan ................................................................................................................................. 279 Capture-DR ........................................................................................................................................ 279 Shift-DR.............................................................................................................................................. 279 Exit1-DR............................................................................................................................................. 279 Pause-DR........................................................................................................................................... 279 Exit2-DR............................................................................................................................................. 279 Update-DR ......................................................................................................................................... 279 Select-IR-Scan ............................................................................................................................... 279 Capture-IR ...................................................................................................................................... 280 Shift-IR............................................................................................................................................ 280 Exit1-IR........................................................................................................................................... 280 Pause-IR......................................................................................................................................... 280 Exit2-IR........................................................................................................................................... 280 Update-IR ....................................................................................................................................... 280 SAMPLE:PRELOAD .......................................................................................................................... 282 BYPASS ............................................................................................................................................. 282 EXTEST ............................................................................................................................................. 282 CLAMP............................................................................................................................................... 282 HIGHZ ................................................................................................................................................ 282 IDCODE ............................................................................................................................................. 282 14.1.1 14.1.2 14.1.3 14.1.4 14.1.5 14.1.6 14.1.7 14.1.8 14.1.9 14.1.10 14.1.11 14.1.12 14.1.13 14.1.14 14.1.15 14.1.16 14.2 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 14.2.6 INSTRUCTION REGISTER...........................................................................................................282 14.3 14.4 14.4.1 14.4.2 14.4.3 JTAG ID CODES......................................................................................................................283 TEST REGISTERS .....................................................................................................................283 Boundary Scan Register .................................................................................................................... 283 Bypass Register ................................................................................................................................. 283 Identification Register......................................................................................................................... 283 15. 16. 17. PIN CONFIGURATION...................................................................................................284 PIN CONFIGURATION--256-BALL TE-CSBGA ..........................................................................284 256-BALL TE-CSBGA (56-G6028-001)...................................................................................285 15.1 16.1 PACKAGE INFORMATION ............................................................................................285 DOCUMENT REVISION HISTORY ................................................................................286 4 of 286 DS26518 8-Port T1/E1/J1 Transceiver LIST OF FIGURES Figure 7-1. Block Diagram ......................................................................................................................................... 18 Figure 7-2. Detailed Block Diagram........................................................................................................................... 19 Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 29 Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 29 Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 29 Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 29 Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 30 Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 30 Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 30 Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 30 Figure 9-9. Backplane Clock Generation................................................................................................................... 31 Figure 9-10. Device Interrupt Information Flow Diagram........................................................................................... 35 Figure 9-11. IBO Multiplexer Equivalent Circuit--4.096MHz .................................................................................... 40 Figure 9-12. IBO Multiplexer Equivalent Circuit--8.192MHz .................................................................................... 41 Figure 9-13. IBO Multiplexer Equivalent Circuit--16.384MHz .................................................................................. 42 Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode............................................................................................... 46 Figure 9-15. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode ................................................................... 46 Figure 9-16. CRC-4 Recalculate Method .................................................................................................................. 70 Figure 9-17. HDLC Message Receive Example........................................................................................................ 76 Figure 9-18. HDLC Message Transmit Example....................................................................................................... 78 Figure 9-19. Network Connection--Longitudinal Protection ..................................................................................... 81 Figure 9-20. T1/J1 Transmit Pulse Templates .......................................................................................................... 84 Figure 9-21. E1 Transmit Pulse Templates ............................................................................................................... 85 Figure 9-22. Receive LIU Termination Options ......................................................................................................... 87 Figure 9-23. Typical Monitor Application ................................................................................................................... 88 Figure 9-24. HPS Block Diagram............................................................................................................................... 90 Figure 9-25. Jitter Attenuation ................................................................................................................................... 91 Figure 9-26. Loopback Diagram ................................................................................................................................ 92 Figure 9-27. Analog Loopback................................................................................................................................... 92 Figure 9-28. Local Loopback ..................................................................................................................................... 93 Figure 9-29. Remote Loopback 2 .............................................................................................................................. 93 Figure 9-30. Dual Loopback ...................................................................................................................................... 94 Figure 11-1. T1 Receive-Side D4 Timing ................................................................................................................ 245 Figure 11-2. T1 Receive-Side ESF Timing.............................................................................................................. 245 Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 246 Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 246 Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 247 Figure 11-6. T1 Receive-Side Interleave Bus Operation--BYTE Mode.................................................................. 248 Figure 11-7. T1 Receive-Side Interleave Bus Operation--FRAME Mode .............................................................. 249 Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit.................................................................... 249 Figure 11-9. T1 Transmit-Side D4 Timing ............................................................................................................... 250 Figure 11-10. T1 Transmit-Side ESF Timing........................................................................................................... 250 Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 251 Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 251 Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 252 Figure 11-14. T1 Transmit-Side Interleave Bus Operation--BYTE Mode............................................................... 253 Figure 11-15. T1 Transmit-Side Interleave Bus Operation--FRAME Mode ........................................................... 254 Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 254 Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 255 5 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 255 Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 256 Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 256 Figure 11-21. E1 Receive-Side Interleave Bus Operation--BYTE Mode ............................................................... 257 Figure 11-22. E1 Receive-Side Interleave Bus Operation--FRAME Mode ............................................................ 258 Figure 11-23. E1 Receive-Side RCHCLKn Gapped Mode During Channel 1 ........................................................ 258 Figure 11-24. E1 Transmit-Side Timing................................................................................................................... 259 Figure 11-25. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 259 Figure 11-26. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 260 Figure 11-27. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 260 Figure 11-28. E1 Transmit-Side Interleave Bus Operation--BYTE Mode .............................................................. 261 Figure 11-29. E1 Transmit-Side Interleave Bus Operation--FRAME Mode ........................................................... 262 Figure 11-30. E1 G.802 Timing ............................................................................................................................... 263 Figure 11-31. E1 Transmit-Side TCHCLKn Gapped Mode During Channel 1 ........................................................ 263 Figure 13-1. SPI Interface Timing Diagram ............................................................................................................. 267 Figure 13-2. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 269 Figure 13-3. Intel Bus Write Timing (BTS = 0)......................................................................................................... 269 Figure 13-4. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 270 Figure 13-5 Motorola Bus Write Timing (BTS = 1) .................................................................................................. 270 Figure 13-6. Receive Framer Timing--Backplane (T1 Mode)................................................................................. 272 Figure 13-7. Receive-Side Timing--Elastic Store Enabled (T1 Mode) ................................................................... 273 Figure 13-8. Receive Framer Timing--Line Side .................................................................................................... 273 Figure 13-9. Transmit Formatter Timing--Backplane ............................................................................................. 275 Figure 13-10. Transmit Formatter Timing--Elastic Store Enabled.......................................................................... 276 Figure 13-11. BPCLK1 Timing................................................................................................................................. 276 Figure 13-12. JTAG Interface Timing Diagram........................................................................................................ 277 Figure 14-1. JTAG Functional Block Diagram ......................................................................................................... 278 Figure 14-2. TAP Controller State Diagram............................................................................................................. 281 6 of 286 DS26518 8-Port T1/E1/J1 Transceiver LIST OF TABLES Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14 Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15 Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16 Table 8-1. Detailed Pin Descriptions ......................................................................................................................... 20 Table 9-1. CLKO Frequency Selection ...................................................................................................................... 32 Table 9-2. Reset Functions........................................................................................................................................ 33 Table 9-3. Registers Related to the Elastic Store...................................................................................................... 36 Table 9-4. Elastic Store Delay After Initialization....................................................................................................... 37 Table 9-5. Registers Related to the IBO Multiplexer ................................................................................................. 39 Table 9-6. RSERn Output Pin Definitions (GTCR1.GIBO = 0).................................................................................. 43 Table 9-7. RSIGn Output Pin Definitions (GTCR1.GIBO = 0) ................................................................................... 43 Table 9-8. TSERn Input Pin Definitions (GTCR1.GIBO = 0) ..................................................................................... 44 Table 9-9. TSIGn Input Pin Definitions (GTCR1.GIBO = 0) ...................................................................................... 44 Table 9-10. RSYNCn Input Pin Definitions (GTCR1.GIBO = 0) ................................................................................ 45 Table 9-11. D4 Framing Mode................................................................................................................................... 48 Table 9-12. ESF Framing Mode ................................................................................................................................ 49 Table 9-13. SLC-96 Framing ..................................................................................................................................... 49 Table 9-14. E1 FAS/NFAS Framing .......................................................................................................................... 51 Table 9-15. Registers Related to Setting Up the Framer .......................................................................................... 52 Table 9-16. Registers Related to the Transmit Synchronizer.................................................................................... 53 Table 9-17. Registers Related to Signaling ............................................................................................................... 54 Table 9-18. Registers Related to SLC-96.................................................................................................................. 57 Table 9-19. Registers Related to T1 Transmit BOC.................................................................................................. 59 Table 9-20. Registers Related to T1 Receive BOC................................................................................................... 59 Table 9-21. Registers Related to T1 Transmit FDL................................................................................................... 60 Table 9-22. Registers Related to T1 Receive FDL.................................................................................................... 60 Table 9-23. Registers Related to E1 Data Link ......................................................................................................... 61 Table 9-24. Registers Related to Maintenance and Alarms...................................................................................... 63 Table 9-25. T1 Alarm Criteria .................................................................................................................................... 65 Table 9-26. Registers Related to Transmit RAI (Yellow Alarm) ................................................................................ 65 Table 9-27. Registers Related to Receive RAI (Yellow Alarm) ................................................................................. 66 Table 9-28. T1 Line Code Violation Counting Options .............................................................................................. 67 Table 9-29. E1 Line Code Violation Counting Options .............................................................................................. 67 Table 9-30. T1 Path Code Violation Counting Arrangements ................................................................................... 68 Table 9-31. T1 Frames Out of Sync Counting Arrangements ................................................................................... 68 Table 9-32. Registers Related to DS0 Monitoring ..................................................................................................... 69 Table 9-33. Registers Related to T1 In-Band Loop Code Generator ........................................................................ 71 Table 9-34. Registers Related to T1 In-Band Loop Code Detection ......................................................................... 72 Table 9-35. Register Related to Framer Payload Loopbacks ................................................................................... 73 Table 9-36. Registers Related to the HDLC .............................................................................................................. 74 Table 9-37. Recommended Supply Decoupling ........................................................................................................ 79 Table 9-38. Registers Related to Control of the LIU.................................................................................................. 82 Table 9-39. Telecommunications Specification Compliance for DS26518 Transmitters .......................................... 83 Table 9-40. Transformer Specifications..................................................................................................................... 83 Table 9-41. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications.............................................................. 89 Table 9-42. Jitter Attenuator Standards Compliance................................................................................................. 91 Table 9-43. Registers Related to Configure, Control, and Status of BERT............................................................... 95 Table 10-1. Register Address Ranges (in Hex)......................................................................................................... 97 Table 10-2. Global Register List ................................................................................................................................ 98 7 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 10-3. Framer Register List ............................................................................................................................... 99 Table 10-4. LIU Register List ................................................................................................................................... 106 Table 10-5. BERT Register List ............................................................................................................................... 106 Table 10-6. Global Register Bit Map........................................................................................................................ 107 Table 10-7. Framer Register Bit Map ...................................................................................................................... 108 Table 10-8. LIU Register Bit Map ............................................................................................................................ 117 Table 10-9. BERT Register Bit Map ........................................................................................................................ 118 Table 10-10. Global Register Set ............................................................................................................................ 119 Table 10-11. Output Status Control ......................................................................................................................... 120 Table 10-12. Master Clock Input Selection.............................................................................................................. 123 Table 10-13. Backplane Reference Clock Select .................................................................................................... 124 Table 10-14. Device ID Codes in this Product Family ............................................................................................. 126 Table 10-15. LIU Register Set ................................................................................................................................. 227 Table 10-16. Transmit Load Impedance Selection.................................................................................................. 229 Table 10-17. Transmit Pulse Shape Selection ........................................................................................................ 229 Table 10-18. Receive Level Indication .................................................................................................................... 234 Table 10-19. Receive Impedance Selection............................................................................................................ 235 Table 10-20. Receiver Sensitivity Selection with Monitor Mode Disabled............................................................... 236 Table 10-21. Receiver Sensitivity Selection with Monitor Mode Enabled ............................................................... 236 Table 10-22. BERT Register Set ............................................................................................................................. 237 Table 10-23. BERT Pattern Select .......................................................................................................................... 239 Table 10-24. BERT Error Insertion Rate ................................................................................................................. 240 Table 10-25. BERT Repetitive Pattern Length Select ............................................................................................. 240 Table 12-1. Recommended DC Operating Conditions ............................................................................................ 264 Table 12-2. Capacitance.......................................................................................................................................... 264 Table 12-3. Recommended DC Operating Conditions ............................................................................................ 264 Table 12-4. Thermal Characteristics........................................................................................................................ 265 Table 12-5. Transmitter Characteristics................................................................................................................... 265 Table 12-6. Receiver Characteristics....................................................................................................................... 265 Table 13-1. SPI Bus Mode Timing........................................................................................................................... 266 Table 13-2. AC Characteristics--Microprocessor Bus Timing ................................................................................ 268 Table 13-3. Receiver AC Characteristics ................................................................................................................ 271 Table 13-4. Transmit AC Characteristics................................................................................................................. 274 Table 13-5. JTAG Interface Timing.......................................................................................................................... 277 Table 14-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 282 Table 14-2. ID Code Structure................................................................................................................................. 283 8 of 286 DS26518 8-Port T1/E1/J1 Transceiver 1. DETAILED DESCRIPTION The DS26518 is an 8-port monolithic device featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each transceiver is composed of a line interface unit, framer, HDLC controller, elastic store, and a TDM backplane interface. The DS26518 is controlled via an 8-bit parallel port or the SPI port. Internal impedance matching and termination is provided for both transmit and receive paths, reducing external component count. The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75 coax and 120 twisted cables. The receive interface provides network termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a T1 or E1 clock rate, or multiple thereof, for both E1 and T1 applications, and can be placed in either transmit or receive data paths. On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receiveside framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock, data, and frame-sync signals to the backplane interface section. Both transmit and receive paths have access to an HDLC controller. The HDLC controller transmits and receives data via the framer block. The HDLC controller can be assigned to any time slot, a portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has 64-byte FIFOs, reducing the amount of processor overhead required to manage the flow of data. The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up to eight transceivers (single DS26518) to share a high-speed backplane. The DS26518 also contains an internal clock adapter useful for the creation of a synchronous, high-frequency backplane timing source. The microprocessor port provides access for configuration and status of all the DS26518's features. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection. 9 of 286 DS26518 8-Port T1/E1/J1 Transceiver 2. 2.1 FEATURE HIGHLIGHTS General 17mm x 17mm, 256-pin TE-CSBGA (1.00mm pitch) 3.3V supply with 5V tolerant inputs and outputs IEEE 1149.1 JTAG boundary scan Development support includes evaluation kit, driver source code, and reference designs 2.2 Line Interface Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz, 2.048MHz, 3.088MHz, 4.096MHz, 6.176MHz, 8.192MHz, 12.352MHz, or 16.384MHz. Fully software configurable Short- and long-haul applications Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB, 0dB to 30dB, 0dB to 20dB, and 0dB to -12dB for T1 Receiver signal level indication from -2.5dB to -36dB in T1 mode and -2.5dB to -44dB in E1 mode in 2.5dB increments Software-selectable receive termination for 75, 100, 110, and 120 lines Hitless protection switching Monitor application gain settings of 14dB, 20dB, 26dB, and 32dB G.703 receive synchronization signal mode Flexible transmit waveform generation T1 DSX-1 line build-outs T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB E1 waveforms include G.703 waveshapes for both 75 coax and 120 twisted cables Analog loss-of-signal detection AIS generation independent of loopbacks Alternating ones and zeros generation Receiver power-down Transmitter power-down Transmit outputs and receive inputs present a high impedance to the line when no power is applied, supporting redundancy applications Transmitter short-circuit limiter with current-limit-exceeded indication Transmit open-circuit-detected indication 2.3 Clock Synthesizers Backplane clocks output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz - Derived from user-selected recovered receive clock or REFCLKIO CLKO output clock selectable from a wide range of frequencies referenced to MCLK 2.4 Jitter Attenuator 32-bit or 128-bit crystal-less jitter attenuator Requires only a 1.544MHz or 2.048MHz master clock or multiple thereof, for both E1 and T1 operation Can be placed in either the receive or transmit path or disabled Limit trip indication 10 of 286 DS26518 8-Port T1/E1/J1 Transceiver 2.5 Framer/Formatter Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats D4 and ESF per T1.403 and expanded SLC-96 support (TR-TSY-008) E1 FAS framing and CRC-4 multiframe per G.704/G.706, and G.732 CAS multiframe Transmit-side synchronizer Transmit midpath CRC recalculate (E1) Detailed alarm and status reporting with optional interrupt support Large path and line error counters - T1: BPV, CV, CRC-6, and framing bit errors - E1: BPV, CV, CRC-4, E-bit, and frame alignment errors - Timed or manual update modes DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths - User defined - Digital Milliwatt ANSI T1.403-1999 support G.965 V5.2 link detect Ability to monitor one DS0 channel in both the transmit and receive paths In-band repeating pattern generators and detectors - Three independent generators and detectors - Patterns from 1 to 8 bits or 16 bits in length Bit oriented code (BOC) support Flexible signaling support - Software or hardware based - Interrupt generated on change of signaling data - Optional receive signaling freeze on loss of frame, loss of signal, or frame slip - Hardware pins provided to indicate loss of frame (LOF), loss of signal (LOS), loss of transmit clock (LOTC), or signaling freeze condition Automatic RAI generation to ETS 300 011 specifications RAI-CI and AIS-CI support Expanded access to Sa and Si bits Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 Japanese J1 support Ability to calculate and check CRC-6 according to the Japanese standard Ability to generate Yellow Alarm according to the Japanese standard T1-to-E1 conversion 2.6 System Interface Independent two-frame receive and transmit elastic stores Independent control and clocking Controlled slip capability with status Minimum delay mode supported Flexible TDM backplane supports bus rates from 1.544MHz to 16.384MHz Supports T1 to CEPT (E1) conversion Programmable output clocks for fractional T1, E1, H0, and H12 applications Interleaving PCM bus operation Hardware signaling capability Receive signaling reinsertion to a backplane multiframe sync Availability of signaling in a separate PCM data stream 11 of 286 DS26518 8-Port T1/E1/J1 Transceiver Signaling freezing Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode User-selectable synthesized clock output 2.7 HDCL Controllers One HDLC controller engine for each T1/E1 port Independent 64-byte Rx and Tx buffers with interrupt support Access FDL, Sa, or single DS0 channel Compatible with polled or interrupt driven environments 2.8 Test and Diagnostics IEEE 1149.1 support Per-channel programmable on-chip bit error-rate testing (BERT) Pseudorandom patterns including QRSS User-defined repetitive patterns Daly pattern Error insertion single and continuous Total-bit and errored-bit counts Payload error insertion Error insertion in the payload portion of the T1 frame in the transmit path Errors can be inserted over the entire frame or selected channels Insertion options include continuous and absolute number with selectable insertion rates F-bit corruption for line testing Loopbacks (remote, local, analog, and per-channel loopback) 2.9 Microcontroller Parallel Port 8-bit parallel control port Intel or Motorola nonmultiplexed support Flexible status registers support polled, interrupt, or hybrid program environments Software reset supported Hardware reset pin Software access to device ID and silicon revision 2.10 Slave Serial Peripheral Interface (SPI) Features Software access to device ID and silicon revision Three-wire synchronous serial data link operating in full-duplex slave mode up to 5Mbps Glueless connection and fully compliant to Motorola popular communication processors such as MPC8260 and microcontrollers such as M68HC11 Software provision ability for active phase of the serial clock (i.e., rising edge vs. falling edge), bit ordering of the serial data (most significant first vs. least significant bit first) Flexible status registers support polled, interrupt, or hybrid program environments 12 of 286 DS26518 8-Port T1/E1/J1 Transceiver 3. APPLICATIONS Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment The DS26518 is useful in applications such as: 13 of 286 DS26518 8-Port T1/E1/J1 Transceiver 4. SPECIFICATIONS COMPLIANCE The DS26518 meets all the latest relevant telecommunications specifications. Table 4-1 provides the T1 specifications and Table 4-2 provides the E1 specifications and relevant sections that are applicable to the DS26518. Table 4-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface AMI Coding B8ZS Substitution Definition DS1 Electrical Interface. Line rate 32ppm; Pulse Amplitude between 2.4V to 3.6V peak; power level between 12.6dBm to 17.9dBm. The T1 pulse mask is provided that we comply. DSX-1 for cross connects the return loss is greater than -26dB. The DSX-1 cable is restricted up to 655 feet. This specification also provides cable characteristics of DSX-Cross Connect cable--22 AVG cables of 1000 feet. ANSI T1.231: Digital Hierarchy--Layer 1 in Service Performance Monitoring BPV Error Definition; Excessive Zero Definition; LOS description; AIS definition. ANSI T1.403: Network and Customer Installation Interface--DS1 Electrical Interface Description of the Measurement of the T1 Characteristics--100. Pulse shape and template compliance according to T1.102; power level 12.4dBm to 19.7dBm when all ones are transmitted. LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB, and -15dB. Line rate is 32ppm. Pulse Amplitude is 2.4V to 3.6V. AIS generation as unframed all ones is defined. The total cable attenuation is defined as 22dB. The DS26518 functions with up to -36dB cable loss. Note that the pulse template defined by T1.403 and T1.102 are different, specifically at Times 0.61, -0.27, -34, and 0.77. The DS26518 is compliant to both templates. Pub 62411 This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter the G.823. (ANSI) "Digital Hierarchy--Electrical Interfaces" (ANSI) "Digital Hierarchy--Formats Specification" (ANSI) "Digital Hierarchy--Layer 1 In-Service Digital Transmission Performance Monitoring" (ANSI) "Network and Customer Installation Interfaces--DS1 Electrical Interface" (AT&T) "Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Super Frame Format" (AT&T) "High Capacity Digital Service Channel Interface Specification" (TTC) "Frame Structures on Primary and Secondary Hierarchical Digital Interfaces" (TTC) "ISDN Primary Rate User-Network Interface Layer 1 Specification" 14 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 4-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate--2048 50ppm; the transmission media are 75 coax or 120 twisted pair; peak-topeak space voltage is 0.237V; nominal pulse width is 244ns. Return loss 51Hz to 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz is 14dB. Nominal peak voltage is 2.37V for coax and 3V for twisted pair. The pulse template for E1 is defined in G.703. ITU-T G.736 Characteristics of Synchronous Digital Multiplex Equipment Operating at 2048kbps The peak-to-peak jitter at 2048kbps must be less than 0.05UI at 20Hz to 100Hz. Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided. ITU-T G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps The DS26518 jitter attenuator is complaint with jitter transfer curve for sinusoidal jitter input. ITU-T G.772 This specification provides the method for using receiver for transceiver 0 as a monitor for the remaining seven transmitter/receiver combinations. ITU-T G.775 An LOS detection criterion is defined. ITU-T G.823 The control of jitter and wander within digital networks that are based on 2.048kbps hierarchy. G.823 Provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz, and 100kHz. ETS 300 233 This specification provides LOS and AIS signal criteria for E1 mode. Pub 62411 This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter than G.823. (ITU-T) "Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44736kbps Hierarchical Levels" (ITU-T) "Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704" (ITU-T) "Characteristics of Primary PCM Multiplex Equipment Operating at 2048kbps" (ITU-T) Characteristics of a Synchronous Digital Multiplex Equipment Operating at 2048kbps" (ITU-T) "Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria" (ITU-T) "The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps Hierarchy" (ITU-T) "Primary Rate User-Network Interface--Layer 1 Specification" (ITU-T) "Error Performance Measuring Equipment Operating at the Primary Rate and Above" (ITU-T) "In-Service Code Violation Monitors for Digital Systems" (ETS) "Integrated Services Digital Network (ISDN); Primary Rate User-Network Interface (UNI); Part 1/Layer 1 Specification" (ETS) "Transmission and Multiplexing; Physical/Electrical Characteristics of Hierarchical Digital Interfaces for Equipment Using the 2048kbps-Based Plesiochronous or Synchronous Digital Hierarchies" (ETS) "Integrated Services Digital Network (ISDN); Access Digital Section for ISDN Primary Rate" (ETS) "Integrated Services Digital Network (ISDN); Attachment Requirements for Terminal Equipment to Connect to an ISDN Using ISDN Primary Rate Access" (ETS) "Business Telecommunications (BT); Open Network Provision (ONP) Technical Requirements; 2048kbps Digital Unstructured Leased Lines (D2048U) Attachment Requirements for Terminal Equipment Interface" (ETS) "Business Telecommunications (BTC); 2048kbps Digital Structured Leased Lines (D2048S); Attachment Requirements for Terminal Equipment Interface" (ITU-T) "Synchronous Frame Structures Used at 1544, 6312, 2048, 8488, and 44736kbps Hierarchical Levels" (ITU-T) "Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704" 15 of 286 DS26518 8-Port T1/E1/J1 Transceiver 5. ACRONYMS AND GLOSSARY This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125s T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. For T1 and E1 each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last. Locked refers to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component). Table 5-1. Time Slot Numbering Schemes TS Channel Phone Channel 0 1 1 2 1 2 3 2 3 4 3 4 5 4 5 6 5 6 7 6 7 8 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 16 of 286 DS26518 8-Port T1/E1/J1 Transceiver 6. MAJOR OPERATING MODES The DS26518 has two major modes of operation: T1 mode and E1 mode. The mode of operation for each LIU is configured in the LTRCR register. The mode of operation for each framer is configured in the TMMR register. J1 operation is a special case of T1 operating mode. 17 of 286 DS26518 8-Port T1/E1/J1 Transceiver 7. BLOCK DIAGRAMS Figure 7-1. Block Diagram DS26518 LIU #8 LIU #7 LIU #6 ... LIU #4 LIU #3 LIU #2 RTIP RTIPE RRING TTIP TRING x8 FRAMER #8 FRAMER #7 FRAMER #6 ... FRAMER #4 FRAMER #3 FRAMER #2 T1/E1 FRAMER LINE INTERFACE UNIT HDLC BERT ELASTIC STORES INTERFACE #8 INTERFACE #7 INTERFACE #6 ... INTERFACE #4 INTERFACE #3 INTERFACE #2 BACKPLANE INTERFACE RECEIVE BACKPLANE SIGNALS TRANSMIT BACKPLANE SIGNALS HARDWARE ALARM INDICATORS x8 MICRO PROCESSOR INTERFACE CLOCK GENERATION JTAG PORT CONTROLLER PORT TEST PORT CLOCK ADAPTER 18 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 7-2. Detailed Block Diagram DS26518 TRANSCEIVER 1 OF 8 Tx BERT Tx HDLC TCHBLK/CLKn TSIGn TTIPn TRANSMIT LIU JITTER ATTENUATOR Waveform Shaper/Line Driver Tx FRAMER: System IF B8ZS/ HDB3 Encode Elastic Store TCLKn TSERn TSYNCn/ TSSYNCIOn TRANSMIT ENABLE BACKPLANE INTERFACE TRINGn LLB FLB PLB TSYSCLKn RSYSCLKn ALB RLB RTIPn RECEIVE LIU Clock/Data Recovery Rx FRAMER: System IF B8ZS/ HDB3 Decode Elastic Store RSYNCn RSERn RCLKn RCHBLK/CLKn RSIGn RM/RFSYNCn RRINGn Rx BERT Rx HDLC MICROPROCESSOR INTERFACE JTAG PORT RESET BLOCK PRE-SCALER PLL CLOCK SYNTHESIZER BPCLK1 REFCLKIO A[12:0] D[7:0] CSB RDB/DSB WRB/RWB BTS SPI_SEL INTB SPI Serial Interface Mode: (SCLK, CPOL, CPHA, SWAP, MOSI, and MISO) JTDO JTDI JTMS JTCLK JTRST 19 of 286 RESETB CLKO MCLK DS26518 8-Port T1/E1/J1 Transceiver 8. 8.1 PIN DESCRIPTIONS Pin Functional Description Table 8-1. Detailed Pin Descriptions NAME TTIP1 TTIP2 TTIP3 TTIP4 TTIP5 TTIP6 TTIP7 TTIP8 TRING1 TRING2 TRING3 TRING4 TRING5 TRING6 TRING7 TRING8 PIN A1, A2 H1, H2 J1 J2 T1, T2 T15, T16 J15, J16 H15, H16 A15, A16 A3, B3 G3, H3 J3, K3 R3, T3 R14,T14 J14, K14 G14, H14 A14, B14 Analog Output, High Impedance Analog Output, High Impedance TYPE FUNCTION ANALOG TRANSMIT Transmit Bipolar Tip for Transceiver 1 to 8. These pins are differential line driver tip outputs. These pins can be high impedance if: If TXENABLE is low, TTIPn/TRINGn will be high impedance. Note that if TXENABLE is low, the register settings for control of TTIPn/TRINGn are ignored and output is high impedance. The differential outputs of TTIPn and TRINGn can provide internal matched impedance for E1 75, E1 120, T1 100, or J1 110. The user can turn off internal termination. Note: The two pins shown for each transmit bipolar tip (e.g., pins A1 and A2 for TTIP1) should be tied together. Transmit Bipolar Ring for Transceiver 1 to 8. These pins are differential line driver ring outputs. These pins can be high impedance if: If TXENABLE is low, TTIPn/TRINGn will be high impedance. Note that if TXENABLE is low, the register settings for control of TTIPn/TRINGn are ignored and output is high impedance. The differential outputs of TTIPn and TRINGn can provide internal matched impedance for E1 75, E1 120, T1 100, or J1 110. The user can turn off internal termination. Note: The two pins shown for each transmit bipolar ring (e.g., pins A3 and B3 for TRING1) should be tied together. Transmit Enable. If this pin is pulled low, all transmitter outputs (TTIPn and TRINGn) are high impedance. The register settings for tri-state control of TTIPn/TRINGn are ignored if TXENABLE is low. If TXENABLE is high, the particular driver can be tri-stated by the register settings. Scan Enable. When low, device is in normal operation. Scan enable is selected by the SCANMODE pin. Note: User should not select scan enable--test mode only. ANALOG RECEIVE C1 F1 L1 P1 P16 L16 F16 C16 C2 F2 L2 P2 P15 L15 F15 C15 J5 TXENABLE/ SCAN_EN L13 Input RTIP1 RTIP2 RTIP3 RTIP4 RTIP5 RTIP6 RTIP7 RTIP8 RRING1 RRING2 RRING3 RRING4 RRING5 RRING6 RRING7 RRING8 RESREF Analog Input Receive Bipolar Tip for Transceiver 1 to 8. The differential inputs of RTIPn and RRINGn can provide internal matched impedance for E1 75, E1 120, T1 100, or J1 110. The user can turn off internal termination via the LIU Receive Impedance and Sensitivity Monitor register (LRISMR). Analog Input Receive Bipolar Ring for Transceiver 1 to 8. The differential inputs of RTIPn and RRINGn can provide internal matched impedance for E1 75, E1 120, T1 100, or J1 110. The user has the option of turning off internal termination via the LIU Receive Impedance and Sensitivity Monitor register (LRISMR). Input Resistor Reference. This pin is used to calibrate the internal impedance match resistors of the receive LIUs. This pin should be tied to VSS through a 10k 1% resistor. 20 of 286 DS26518 8-Port T1/E1/J1 Transceiver NAME TSER1 TSER2 TSER3 TSER4 TSER5 TSER6 TSER7 TSER8 TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 TCLK8 PIN F6 E7 R4 N7 M10 L11 F10 D12 C5 D7 P5 L8 L10 N11 E10 B13 TYPE TRANSMIT FRAMER Transmit NRZ Serial Data 1 to 8. These pins are sampled on the falling edge of TCLKn when the transmit-side elastic store is disabled. These pins are sampled on the falling edge of TSYSCLKn when the transmit-side elastic store is enabled. In IBO mode, data for multiple framers can be used in high-speed multiplexed scheme. This is described in Section 9.8.2. The table there presents the combination of framer data for each of the streams. TSYSCLKn is used as a reference when IBO is invoked. See Table 9-8. FUNCTION Input Input Transmit Clock 1 to 8. A 1.544MHz or a 2.048MHz primary clock. Used to clock data through the transmit side of the transceiver. TSERn data is sampled on the falling edge of TCLKn. TCLKn is used to sample TSERn when the elastic store is not enabled or IBO is not used. TSYSCLK1 P13 Input Transmit System Clock 1. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic store function is enabled. Should be tied low in applications that do not use the transmit-side elastic store. The clock can be 4.096MHz, 8.912MHz, or 16.384MHz when IBO mode is used. TSYSCLK1 does not have an internal pulldown resistor. Note: If the GTCR1.528MD bit is set, TSYSCLK1 becomes the master TSYSCLK for all framers. Transmit System Clock 2 to 8. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic store function is enabled. Should be tied low in applications that do not use the transmit-side elastic store. The clock can be 4.096MHz, 8.912MHz, or 16.384MHz when IBO mode is used. TSYSCLK1 does not have an internal pulldown resistor. Note: If the GTCR1.528MD bit is set, TSYSCLK1 becomes the master TSYSCLK for all framers. Analog Loss/Receive-Signaling Freeze/Framer LOS. Analog LOS reflects the LOS (loss of signal) detected by the LIU front-end and framer LOS is LOS detection by the corresponding framer; the same pins can reflect receivesignaling freeze indications. This selection can be made by settings in the Global Transceiver Clock Control Register 1 (GTCCR1). AL/RSIGF/FLOS[8:2] is available only by setting the GTCR1.528MD bit to 1. Transmit Synchronization 1 to 8. A pulse at these pins establishes either frame or multiframe boundaries for the transmit side. These signals can also be programmed to output either a frame or multiframe pulse. If these pins are set to output pulses at frame boundaries, they can also be set to output double-wide pulses at signaling frames in T1 mode. The operation of these signals is synchronous with TCLK[8:1]. Transmit System Synchronization In. These pins are selected when the transmit-side elastic store is enabled. A pulse at these pins establishes either frame or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the transmit-side elastic store. The operation of this signal is synchronous with TSYSCLK[8:1]. Transmit System Synchronization Out. If configured as an output and the transmit elastic store is enabled, an 8kHz pulse synchronous to the BPCLK1 will be generated. This pulse in combination with BPCLK1 can be used as an IBO master. TSSYNCIOn can be used as a source to RSYNCn and TSSYNCIOn of another DS26518 or RSYNC and TSSYNC of other Dallas Semiconductor parts. Note: TSSYNCIO[8:1] are not used when GTCR1.528MD is set. When GTCR1.528MD is set, the TSSYNCIO pin (N13) is used. TSYSCLK2/ AL/RSIGF/FLOS2 TSYSCLK3/ AL/RSIGF/FLOS3 TSYSCLK4/ AL/RSIGF/FLOS4 TSYSCLK5/ AL/RSIGF/FLOS5 TSYSCLK6/ AL/RSIGF/FLOS6 TSYSCLK7/ AL/RSIGF/FLOS7 TSYSCLK8/ AL/RSIGF/FLOS8 TSYNC1/ TSSYNCIO1 TSYNC2/ TSSYNCIO2 TSYNC3/ TSSYNCIO3 TSYNC4/ TSSYNCIO4 TSYNC5/ TSSYNCIO5 TSYNC6/ TSSYNCIO6 TSYNC7/ TSSYNCIO7 TSYNC8/ TSSYNCIO8 F3 L3 P3 P14 L14 F14 C14 B4 F7 M6 M7 N10 T12 B11 Input/ Output Input with internal pulldown/ Output A13 21 of 286 DS26518 8-Port T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION Note: In default operation, this pin is not used. When GTCR1.528MD is set, this pin is active. If pin is not used, tie low through a resistor. Transmit System Synchronization In. This pin is selected when the transmitside elastic store is enabled. A pulse at this pin establishes either frame or multiframe boundaries for the transmit side. Note that if the elastic store is enabled, frame or multiframe boundary will be established for all transmitters. Should be tied low in applications that do not use the transmit-side elastic store. The operation of this signal is synchronous with TSYSCLKn. Transmit System Synchronization Out. If configured as an output and the transmit-side elastic store is enabled, an 8kHz pulse synchronous to BPCLK1 will be generated. This pulse in combination with BPCLK1 can be used as an IBO master. TSSYNCIO can be used as a source to RSYNCn and TSSYNCIO of another DS26518 or RSYNC and TSSYNC of other Dallas Semiconductor parts. TSIG1 TSIG2 TSIG3 TSIG4 TSIG5 TSIG6 TSIG7 TSIG8 TCHBLK1/ TCHCLK1 TCHBLK2/ TCHCLK2 TCHBLK3/ TCHCLK3 TCHBLK4/ TCHCLK4 TCHBLK5/ TCHCLK5 TCHBLK6/ TCHCLK6 TCHBLK7/ TCHCLK7 TCHBLK8/ TCHCLK8 D5 A6 T4 R6 T10 R12 A11 C13 A5 C7 L7 P7 Output P9 P11 D10 E11 TSSYNCIO N13 Input/ Output Input Transmit Signaling 1 to 8. When enabled, this input samples signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLKn when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLKn when the transmit-side elastic store is enabled. In IBO mode, the TSIGn streams can run up to 16.384MHz. See Table 9-9. Transmit Channel Block/Transmit Channel Block Clock. A dual function pin. TCHBLK[1:8]. TCHBLKn is a user-programmable output that can be forced high or low during any of the channels. It is synchronous with TCLKn when the transmit-side elastic store is disabled. It is synchronous with TSYSCLKn when the transmit-side elastic store is enabled. It is useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external perchannel loopback, and for per-channel conditioning. TCHCLK[1:8]. TCHCLKn is a 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. It can also be programmed to output a gated transmit bit clock controlled by TCHBLKn. It is synchronous with TCLKn when the transmit-side elastic store is disabled. It is synchronous with TSYSCLKn when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data. 22 of 286 DS26518 8-Port T1/E1/J1 Transceiver NAME RSER1 RSER2 RSER3 RSER4 RSER5 RSER6 RSER7 RSER8 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 PIN E5 D6 N4 N6 M11 M12 B12 F11 F4 G4 L4 M4 K13 J13 F13 E13 TYPE RECEIVE FRAMER Received Serial Data 1 to 8. Received NRZ serial data. Updated on rising edges of RCLKn when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLKn when the receive-side elastic store is enabled. When IBO mode is used, the RSERn pins can output data for multiple framers. The RSERn data is synchronous to RSYSCLKn. See Section 9.8.2 and Table 9-6. FUNCTION Output Output Receive Clock 1 to 8. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer. This clock is recovered from the signal at RTIPn and RRINGn. RSERn data is output on the rising edge of RCLKn. RCLKn is used to output RSERn when the elastic store is not enabled or IBO is not used. When the elastic store is enabled or IBO is used, the RSERn is clocked by RSYSCLKn. RSYSCLK1 L12 Input Receive System Clock 1. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz receive backplane clock. Only used when the receive-side elastic store function is enabled. Should be tied low in applications that do not use the receive-side elastic store. Multiple of 2.048MHz is expected when the IBO mode is used. Note: If the GTCR1.528MD bit is set, RSYSCLK1 becomes the master RSYSCLK for all framers. Receive System Clock 2 to 8. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz receive backplane clock. Only used when the receive-side elastic store function is enabled. Should be tied low in applications that do not use the receive-side elastic store. Multiple of 2.048MHz is expected when the IBO Mode is used. Receive Loss of Frame/Loss of Transmit Clock. This pin can also be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLKn pin has not been toggled for approximately three clock periods. RLF/LTC[8:2] are available when GTCR1.528MD = 1. Note: If the GTCR1.528MD bit is set, RSYSCLK1 becomes the master RSYSCLK for all framers. Receive Synchronization 1 to 8. If the receive-side elastic store is enabled, this signal is used to input a frame or multiframe boundary pulse. If set to output frame boundaries, RSYNCn can be programmed to output double-wide pulses on signaling frames in T1 mode. In E1 mode, RSYNCn out can be used to indicate CAS and CRC-4 multiframe. The DS26518 can accept an H.100-compatible synchronization signal. The default direction of this pin at power-up is input, as determined by the RSIO control bit in the RIOCR.2 register. RSYSCLK2/ RLF/LTC2 RSYSCLK3/ RLF/LTC3 RSYSCLK4/ RLF/LTC4 RSYSCLK5/ RLF/LTC5 RSYSCLK6/ RLF/LTC6 RSYSCLK7/ RLF/LTC7 RSYSCLK8/ RLF/LTC8 RSYNC1 RSYNC2 RSYNC2 RSYNC2 RSYNC5 RSYNC6 RSYNC7 RSYNC8 E3 M3 N3 N14 M14 E14 D14 A4 B6 N5 T6 R10 P12 C11 D13 Input with internal pulldown/ Output Input/ Output 23 of 286 DS26518 8-Port T1/E1/J1 Transceiver NAME RMSYNC1/ RFSYNC1 RMSYNC2/ RFSYNC2 RMSYNC3/ RFSYNC3 RMSYNC4/ RFSYNC4 RMSYNC5/ RFSYNC5 RMSYNC6/ RFSYNC6 RMSYNC7/ RFSYNC7 RMSYNC8/ RFSYNC8 RSIG1 RSIG2 RSIG3 RSIG4 RSIG5 RSIG6 RSIG7 RSIG8 RCHBLK1/ RCHCLK1 RCHBLK2/ RCHCLK2 RCHBLK3/ RCHCLK3 RCHBLK4/ RCHCLK4 RCHBLK5/ RCHCLK5 RCHBLK6/ RCHCLK6 RCHBLK7/ RCHCLK7 RCHBLK8/ RCHCLK8 PIN C4 C6 P4 P6 Output P10 N12 D11 E12 D4 E6 M5 R5 R11 R13 A12 F12 E4 B5 L6 T5 Output T11 T13 C12 G13 Receive Multiframe/Frame Synchronization 1 to 8. A dual function pin to indicate frame or multiframe synchronization. RFSYNCn is an extracted 8kHz pulse, one RCLKn wide that identifies frame boundaries. RMSYNCn is an extracted pulse, one RCLKn wide (elastic store disabled) or one RSYSCLKn wide (elastic store enabled), that identifies multiframe boundaries. When the receive elastic store is enabled, the RMSYNCn signal indicates the multiframe sync on the system (backplane) side of the elastic store. In E1 mode, this pin can indicate either the CRC-4 or CAS multiframe as determined by the RSMS2 control bit in the Receive I/O Configuration register (RIOCR.1). TYPE FUNCTION Output Receive Signaling 1 to 8. Outputs signaling bits in a PCM format. Updated on rising edges of RCLKn when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLKn when the receive-side elastic store is enabled. See Table 9-7. Receive Channel Block/Receive Channel Block Clock. This pin can be configured to output either RCHBLK or RCHCLK. RCHBLK[1:8]. RCHBLKn is a user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. It is synchronous with RCLKn when the receive-side elastic store is disabled. It is synchronous with RSYSCLKn when the receive-side elastic store is enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. RCHCLK[1:8]. RCHCLKn is a 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. It is synchronous with RCLKn when the receiveside elastic store is disabled. It is synchronous with RSYSCLKn when the receive-side elastic store is enabled. It is useful for parallel-to-serial conversion of channel data. Backplane Clock 1. Programmable clock output that can be set to 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK[8:1], a 1.544MHz or 2.048MHz clock frequency derived from MCLK, or an external reference clock (REFCLKIO). This allows system clocks to be referenced from external sources, the T1J1E1 recovered clocks, or the MCLK oscillator. Clock Out. Clock output pin that can be programmed to output numerous frequencies referenced to MCLK. Frequencies available: 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 12.288MHz, 16.384MHz, 256kHz, and 64kHz. GTCCR3.CLKOSEL[2:0] selects the frequency. Receive Loss of Frame/Loss of Transmit Clock. This pin can also be programmed to either toggle high when the synchronizer is searching for the frame and multiframe, or to toggle high if the TCLKn pin has not been toggled for approximately three clock periods. RLF/LTC1 is available on the DS26518 when GTCR1.528MD = 1. BPCLK1 E8 Output CLKO/ RLF/LTC1 D3 Output 24 of 286 DS26518 8-Port T1/E1/J1 Transceiver NAME A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PIN C8 A8 B8 F8 B9 A9 C9 D9 E9 F9 B10 A10 C10 TYPE MICROPROCESSOR INTERFACE FUNCTION Input Address [12:0]. This bus selects a specific register in the DS26518 during read/write access. A12 is the MSB and A0 is the LSB. D[7]/SPI_CPOL T9 Input/ Output Data [7]/SPI Interface Clock Polarity D[7]: Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes and data outputs during register reads. Not driven when CSB = 1. SPI_CPOL: This signal selects the clock polarity when SPI_SEL = 1. See Section 9.1.2 for detailed timing and functionality information. Default setting is low. Data [6]/SPI Interface Clock Phase D[6]: Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes and data outputs during register reads. Not driven when CSB = 1. SPI_CPHA: This signal selects the clock phase when SPI_SEL = 1. See Section 9.1.2 for detailed timing and functionality information. Default setting is low. Data [5]/SPI Bit Order Swap D[5]: Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes and data outputs during register reads. Not driven when CSB = 1. D[6]/SPI_CPHA N9 Input/ Output D[5]/SPI_SWAP M9 Input/ Output D[4] D[3] R8 T8 Input/ Output Input/ Output Input/ Output SPI_SWAP: This signal is active when SPI_SEL = 1. The address and data bit order is swapped when SPI_SWAP is high. The R/W and B bit positions are never changed in the control word. 0 = LSB is transmitted and received first. 1 = MSB is transmitted and received first. Data [4]. Bit 4 of the 8-bit data bus used to input data during register writes and data outputs during register reads. Not driven when CSB = 1. Data [3]. Bit 3 of the 8-bit data bus used to input data during register writes and data outputs during register reads. Not driven when CSB = 1. Data [2]/SPI Serial Interface Clock D[2]: Bit 2 of the 8-bit data bus used to input data during register writes and data outputs during register reads. Not driven when CSB = 1. SPI_SCLK: SPI Serial Clock Input when SPI_SEL = 1. Data [1]/SPI Serial Interface Data Master Out-Slave In D[1]: Bit 1 of the 8-bit data bus used to input data during register writes, and data outputs during register reads. Not driven when CSB = 1. SPI_MOSI: SPI Serial Data Input (Master Out-Slave In) when SPI_SEL = 1. Data [0]/SPI Serial Interface Data Master In-Slave Out D[2]/SPI_SCLK P8 D[1]/SPI_MOSI L9 Input/ Ouput D[0]/SPI_MISO N8 Input/ Output D[0]: Bit 0 of the 8-bit data bus used to input data during register writes and data outputs during register reads. Not driven when CSB = 1. SPI_MISO: SPI Serial Data Output (Master In-Slave Out) when SPI_SEL = 1. CSB RDB/ DSB T7 Input Chip-Select Bar. This active-low signal is used to qualify register read/write accesses. The RDB/DSB and WRB signals are qualified with CSB. Read-Data Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies read access to one of the DS26518 registers. The DS26518 drives the data bus with the contents of the addressed register while RDB and CSB are low. M8 Input 25 of 286 DS26518 8-Port T1/E1/J1 Transceiver NAME WRB/ RWB PIN R7 TYPE Input Output, TriStateable FUNCTION Write-Read Bar/Read-Write Bar. This active-low signal along with CSB qualifies write access to one of the DS26518 registers. Data at D[7:0] is written into the addressed register at the rising edge of WRB while CSB is low. Interrupt Bar. This active-low output is asserted when an unmasked interrupt event is detected. INTB will be deasserted (and tri-stated) when all interrupts have been acknowledged and serviced. Extensive mask bits are provided at the global level, framer, LIU, and BERT level. SPI Serial Bus Mode Select/Analog Loss/Receive Signaling Freeze/Framer LOS SPI_SEL: 0 = Parallel Bus Mode, 1 = SPI Serial Bus Mode AL/RSIGF/FLOS1: Analog LOS reflects the loss of signal detected by the LIU front-end; framer LOS is LOS detection by the corresponding framer. The same pins can reflect receive-signaling freeze indications. This selection can be made by settings in Global Transceiver Control Register (GTCR1). AL/RSIGF/FLOS1 are available by setting the GTCR1.528MD bit to 1. Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus timing. This pin controls the function of the RDB/DSB and WRB pins. Note: If SPI mode is selected by the SPI_SEL pin, this pin must be tied low. SYSTEM INTERFACE Master Clock. This is an independent free-running clock whose input can be a multiple of 2.048MHz 50ppm or 1.544MHz 50ppm. The clock selection is available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to 2.048MHz. Note that TCLKn must be 2.048MHz for E1 and 1.544MHz for T1/J1 operation. See Table 10-12. Reset Bar. Active-low reset. This input forces the complete DS26518 reset. This includes reset of the registers, framers, and LIUs. Reference Clock Input/Output Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate the backplane clock. This allows for the users to synchronize the system backplane with the reference clock. The other options for the backplane clock reference are LIU-received clocks or MCLK. Output: This signal can also be used to output a 1.544MHz or 2.048MHz reference clock. This allows for multiple DS26518s to share the same reference for generation of the backplane clock. Hence, in a system consisting of multiple DS26518s, one can be a master and others a slave using the same reference clock. TEST DIGIOEN D8 Input, Pullup Digital Enable. When this pin and JTRST are pulled low, all digital I/O pins are placed in a high-impedance state. If this pin is high the digital I/O pins operate normally. This pin must be connected to VDD for normal operation. JTAG Reset. JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This action sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal device operation. JTRST is pulled high internally via a 10k resistor operation. If boundary scan is not used, this pin should be held low. JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1 states. This pin has a 10k pullup resistor. JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. JTAG Data In. Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pullup resistor. JTAG Data Out. Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected. INTB R9 SPI_SEL/ AL/RSIGF/FLOS1 C3 Input with internal pulldown/ Output BTS M13 Input MCLK B7 Input RESETB J12 Input REFCLKIO A7 Input/ Output JTRST L5 Input, Pullup JTMS JTCLK JTDI JTDO K4 F5 H4 J4 Input, Pullup Input Input, Pullup Output, High Impedance 26 of 286 DS26518 8-Port T1/E1/J1 Transceiver NAME SCANMODE PIN H13 TYPE Input FUNCTION Scan Mode. When low, normal operational clocks are used to clock the flip flops. User should tie low. POWER SUPPLIES ATVDD B1, B16, G1, G16, K1, K16, R1, R16 B2, B15, G2, G15, K2, K15, R2, R15 D1, D16, E1, E16, M1, M16, N1, N16 D2, D15, E2, E15, M2, M15, N2, N15 H7 J7 G5, G6, G11, G12, H5, H6, H8, H9, H10, H11 G7-G10 H12, J6, J8-J11, K5-K12 -- 3.3V 5% Analog Transmit Power Supply. These VDD inputs are used for the transmit LIU sections of the DS26518. ATVSS -- Analog Transmit VSS. These pins are used for transmit analog VSS. ARVDD -- 3.3V 5% Analog Receive Power Supply. These VDD inputs are used for the receive LIU sections of the DS26518. ARVSS -- Analog Receive VSS. These pins are used for analog VSS for the receivers. 1.8V 5% Analog Clock Conversion VDD. This VDD input is used for the clock conversion unit (CLAD) of the DS26518. Analog Clock VSS. This pin is used for clock converter analog VSS. ACVDD ACVSS -- -- DVDD33 -- 3.3V 5% Power Supply for I/Os DVDD18 -- 1.8V 5% Power Supply for Internal VDD DVSS -- Digital Ground 27 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9. 9.1 FUNCTIONAL DESCRIPTION Processor Interface Microprocessor control of the DS26518 is accomplished through the 28 hardware pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select (BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in Figure 13-2 and Figure 13-3. When the BTS pin is a logic 1, bus timing is in Motorola mode, as shown in Figure 13-4 and Figure 13-5. The address space is mapped through the use of 13 address lines, A[12:0]. Multiplexed mode is not supported on the processor interface. The chip-select bar (CSB) pin must be brought to a logic-low level to gain read and write access to the microprocessor port. With Intel timing selected, the read-data bar (RDB) and write-read bar (WRB) pins are used to indicate read and write operations and latch data through the interface. With Motorola timing selected, the readwrite bar (RWB) pin is used to indicate read and write operations while the data-strobe bar (DSB) pin is used to latch data through the interface. The interrupt output pin (INTB) is an open-drain output that asserts a logic-low level upon a number of software maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. 9.1.1 SPI Serial Port Mode The external processor bus can be configured to operate in SPI serial bus mode. See Section 9.1.2 for detailed timing diagrams. When SPI_SEL = 1, SPI bus mode is implemented using four signals: clock (SPI_SCLK), master out-slave in data (SPI_MOSI), master in-slave out data (SPI_MISO), and chip select (CSB). Clock polarity and phase can be set by the D[7]/SPI_CPOL and D[6]/SPI_CPHA pins. The order of the address and data bits in the serial stream is selectable using the D[5]/SPI_SWAP pin. The R/W bit is always first and B bit is always last in the initial control word and are not effected by the D[5]/SPI_SWAP pin setting. SPI mode is not recommended for HDLC operations because of the bandwidth constraints of SPI. 9.1.2 SPI Functional Timing Diagrams Note: The transmit and receive order of the address and data bits are selected by the D[5]/SPI_SWAP pin. The R/W (read/write) MSB bit and B (burst) LSB bit position is not affected by the D[5]/SPI_SWAP pin setting. 9.1.2.1 SPI Transmission Format and CPHA Polarity When SPI_CPHA = 0, CSB may be deasserted between accesses. An access is defined as one or two control bytes followed by a data byte. CSB cannot be deasserted between the control bytes, or between the last control byte and the data byte. When SPI_CPHA = 0, CSB may also remain asserted between accesses. If it remains asserted and the BURST bit is set, no additional control bytes are expected after the first control byte(s) and data are transferred. If the BURST bit is set, the address will be incremented for each additional byte of data transferred until CSB is deasserted. If CSB remains asserted and the BURST bit is not set, a control byte(s) is expected following the data byte, and the address for the next access will be received from that. Anytime CSB is deasserted, the BURST access is terminated. When SPI_CPHA = 1, CSB may remain asserted for more than one access without being toggled high and then low again between accesses. If the BURST bit is set, the address should increment and no additional control bytes are expected. If the BURST bit is not set, each data byte will be followed by the control byte(s) for the next access. Additionally, CSB may also be deasserted between accesses when SPI_CPHA = 1. In the case, any BURST access is terminated and the next byte received when CSB is reasserted will be a control byte. The following diagrams describe the functionality of the SPI port for the four combinations of SPI_CPOL and SPI_CPHA. They indicate the clock edge that samples the data and the level of the clock during no-transfer events (high or low). Since the SPI port of the DS26518 acts as a slave device, the master device provides the clock. The 28 of 286 DS26518 8-Port T1/E1/J1 Transceiver user must configure the SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is providing. Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 SPI_SCLK CSB SPI_MOSI 1 MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 MSB A5 A4 A3 A2 A1 A0 B LSB D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB SPI_MISO Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 SPI_SCLK CSB SPI_MOSI 1 MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 MSB A5 A4 A3 A2 A1 A0 B LSB D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB SPI_MISO Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 SPI_SCLK CSB SPI_MOSI 1 MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 MSB A5 A4 A3 A2 A1 A0 B LSB D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB SPI_MISO Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 SPI_SLCK CSB SPI_MOSI 1 MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 MSB A5 A4 A3 A2 A1 A0 B LSB D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB SPI_MISO 29 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 SPI_SCLK CSB SPI_MOSI SPI_MISO 0 MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 MSB A5 A4 A3 A2 A1 A0 B LSB D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 SPI_SCLK CSB SPI_MOSI SPI_MISO 0 MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 MSB A5 A4 A3 A2 A1 A0 B LSB D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 SPI_SCLK CSB SPI_MOSI 0 MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 MSB A5 A4 A3 A2 A1 A0 B LSB D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB SPI_MISO Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 SPI_SCLK CSB SPI_MOSI SPI_MISO 0 MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 MSB A5 A4 A3 A2 A1 A0 B LSB D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB 30 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.2 Clock Structure The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1 and E1 frequencies. To meet many specifications, the MCLK source should have 50ppm accuracy. 9.2.1 Backplane Clock Generation The DS26518 provides facility for provision of BPCLK1 at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see Figure 9-9). The Global Transceiver Clock Control Register 1 (GTCCR1) is used to control the backplane clock generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can be an output sourcing MCLKT1 or MCLKE1 as shown in Figure 9-9. This backplane clock and frame pulse (TSSYNCIOn) can be used by the DS26518 and other IBO-equipped devices as an "IBO Bus Master." Hence, the DS26518 provides the 8kHz sync pulse and 4MHz, 8MHz, and 16MHz clock. This can be used by the link layer devices and frames connected to the IBO bus. Figure 9-9. Backplane Clock Generation BPREFSEL3:0 BPCLK1:0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 MCLK Pre Scaler PLL MCLKT1 MCLKE1 REFCLKIO Clock Multiplexor BFREQSEL CLK GEN BPCLK TSSYNCIO REFCLKIO The reference clock for the backplane clock generator can be as follows: * External Master Clock. A prescaler can be used to generate T1 or E1 frequency. * External Reference Clock REFCLKIO. This allows for multiple DS26518s to use the backplane clock from a common reference. * Internal LIU recovered RCLKs 1 to 8. * The clock generator can be used to generate BPCLK1 of 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz for the IBO. * If MCLK or RCLKn is used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz clock for external use. 31 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.2.2 CLKO Output Clock Generation This clock output is derived from MCLK based upon the setting of the CLKOSEL[2:0] bits in the GTCCR3 register.The reference for the PLL is not the input clock on MCLK, but the scaled version of MCLK (1.544MHz or 2.048MHz). The LTRCR.T1J1E1S bit also selects the proper PLL for use in generating the appropriate frequency. This clock output pin is provided as an additional feature to eliminate the need for another board oscillator. Table 9-1. CLKO Frequency Selection CLKOSEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLKO (kHz) 2048 4096 8192 16384 1544 3088 6176 12352 1536 3072 6144 12288 32 64 128 256 32 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.3 Resets and Power-Down Modes A hardware reset is issued by forcing the RESETB pin to logic low. The RESETB input pin resets all framers, LIUs, and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing reserved locations to 00h. Table 9-2. Reset Functions RESET FUNCTION Hardware Device Reset Hardware JTAG Reset Global Software Reset Framer Receive Reset Framer Transmit Reset HDLC Receive Reset HDLC Transmit Reset Elastic Store Receive Reset Elastic Store Transmit Reset Bit Oriented Code Receive Reset Loop Code Integration Reset Spare Code Integration Reset LOCATION RESETB Pin JTRST Pin GSRR1 RMMR.1 TMMR.1 RHC.6 THC1.5 RESCR.2 TESCR.2 T1RBOCC.7 T1RDNCD1, T1RUPCD1 T1RSCD1 COMMENTS Transition to a logic 0 level resets the DS26518. Resets the JTAG test port. Writing to this register resets the framers, LIUs and BERTs (transmit and receive). Writing to this bit resets the receive framer. Writing to this bit resets the transmit framer. Writing to this bit resets the receive HDLC controller. Writing to this bit resets the transmit HDLC controller. Writing to this bit resets the receive elastic store. Writing to this bit resets the transmit elastic store. Writing to this bit resets the receive BOC controller. Writing to these registers resets the programmable in-band code integration period. Writing to this register resets the programmable in-band code integration period. The DS26518 has several features included to reduce power consumption. The individual LIU transmitters can be powered down by setting the TPDE bit in the LIU Maintenance Control Register (LMCR). Note that powering down the transmit LIU results in a high-impedance state for the corresponding TTIPn and TRINGn pins and reduced operating current. The RPDE in the LMCR register can be used to power down the LIU receiver. The TE (transmit enable) bit in the LMCR register can be used to disable the TTIPn and TRINGn outputs and place them in a high-impedance mode, while keeping the LIU in an active state (powered up). This is useful for equipment protection-switching applications. 33 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.4 9.4.1 Initialization and Configuration Example Device Initialization and Sequence STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device, or by using the software reset bits outlined in Section 9.2.2. Clear all reset bits. Allow time for the reset recovery. STEP 2: Check the Device ID in the IDR register. STEP 3: Write the GTCCR1 register to correctly configure the system clocks. If supplying a 1.544MHz MCLK follows this write with at least a 300ns delay in order to allow the clock system to properly adjust. STEP 4: Write the entire remainder of the register space for each port with 00h, including reserved register locations. STEP 5: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the TMMR and RMMR registers for each framer. Set the FRM_EN bit to 1 in the TMMR and RMMR registers. If using software transmit signaling in E1 mode, program the E1TAF and E1TNAF registers as required. Configure the framer Transmit Control Registers (TCR1-TCR4). Configure the framer Receive Control Registers (RCR1-RCR3). Configure other framer features as appropriate. STEP 6: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the LTRCR register. Configure the line build-out for each LIU. Configure other LIU features as appropriate. Set the TE (transmit enable) bit to turn on the TTIPn and TRINGn outputs. STEP 7: Configure the elastic stores, HDLC controller, and BERT as needed. STEP 8: Set the INIT_DONE bit in the TMMR and RMMR registers for each framer. 9.5 Global Resources All eight framers share a common microprocessor port and a common MCLK. There is a common software configurable BPCLK1 output. A set of global registers includes global resets, global interrupt status, interrupt masking, clock configuration, and the device ID register. See the global register bit map in Table 10-6. A common JTAG controller is used for all ports. 9.6 Per-Port Resources Each port has an associated framer, LIU, BERT, jitter attenuator, and transmit/receive HDLC controller. Each of the per-port functions has its own register space. 9.7 Device Interrupts Figure 9-10 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global interrupt information registers GFISR1, GLISR1, and GBISR1 to quickly identify which of the eight transceivers is (are) causing the interrupt(s). The host can then read the specific transceiver's interrupt information registers (TIIR, RIIR) and the latched status registers (LLSR, BLSR) to further identify the source of the interrupt(s). If TIIR or RIIR is the source, the host reads the transmit latched status or the receive latched status registers for the source of the interrupt. All interrupt information register bits are real-time bits that clear once the appropriate interrupt has been serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated status register. All latched status bits must be cleared by the host writing a "1" to the bit location of the interrupt condition that has been serviced. Latched status bits that have been masked via the interrupt mask registers are masked from the interrupt information registers. The interrupt mask register bits prevent individual latched status conditions from generating an interrupt, but they do not prevent the latched status bits from being set. Therefore, when servicing interrupts, the user should XOR the latched status with the associated interrupt mask in order to exclude bits for which the user wished to prevent interrupt service. This architecture allows the application host to periodically poll the latched status bits for noninterrupt conditions, while using only one set of registers. 34 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-10. Device Interrupt Information Flow Diagram Receive Remote Alarm Indication Clear Receive Alarm Condition Clear Receive Loss of Signal Clear Receive Loss of Frame Clear Receive Remote Alarm Indication Receive Alarm Condition Receive Loss of Signal Receive Loss of Frame Receive Signal All Ones Receive Signal All Zeros Receive CRC4 Multiframe Receive Align Frame Loss of Receive Clk Clear / Loss of Receive Clk Clear Spare Code Detected Condition Clear / Loop Down Code Clear / V52 Link Clear Loop Up Code Clear / Receive Distant MF Alarm Clear Loss of Receive Clk / Loss of Receive Clk Spare Code Detect / Loop Down Detect / V52 Link Detect Loop Up Detect / Receive Distant MF Alarm Detect Receive Elastic Store Full Receive Elastic Store Empty Receive Elastic Store Slip Receive Signaling Change of State (Enable in RSCSE1-4) One Second Timer Timer Receive Multiframe Receive FIFO Overrun Receive HDLC Opening Byte Receive Packet End Receive Packet Start Receive Packet High Watermark Receive FIFO Not Empty Receive RAI-CI Receive AIS-CI Receive SLC-96 Alignment Receive FDL Register Full Receive BOC Clear Receive BOC Transmit Elastic Store Full Transmit Elastic Store Empty Transmit Elastic Store Slip Transmit SLC96 Multiframe Transmit Align Frame Transmit Multiframe Loss of Transmit Clock Clear Loss of Transmit Clock Transmit FDL Register Empty Transmit FIFO Underrun Transmit Message End Transmit FIFO Below Low Watermark Transmit FIFO Not Full Set Loss of Frame Loss of Frame Synchronization Jitter Attenuator Limit Trip Clear Open Circuit Detect Clear Short Circuit Detect Clear Loss of Signal Detect Clear Jitter Attenuator Limit Trip Open Circuit Detect Short Circuit Detect Loss of Signal Detect BERT Bit Error Detected BERT Bit Counter Overflow BERT Error Counter Overflow BERT Receive All Ones BERT Receive All Zeros BERT Receive Loss of Synchronization BERT in Synchronization 7 6 5 4 3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4 3 2 1 0 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Drawing Legend: RLS1 RIM1 0 Interrupt Status Registers Interrupt Mask Registers Register Name RIM2 RLS 2 1 Register Name RLS3 RIM3 2 RLS4 RIM4 3 RLS5 RIM5 4 RLS7 RIM7 RIIR Framers 2-8 5 TLS1 2 TLS2 TIM2 1 LSIMR LLSR 0 BLSR BSIM 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 GFIMR1 GFISR1 TIM1 35 of 286 BERTs 2-8 GBIMR1 GBISR1 Interrupt Pin TIIR LIUs 2-8 GLIMR1 GTCR1.0 GLISR1 TLS3 TIM3 DS26518 8-Port T1/E1/J1 Transceiver 9.8 System Backplane Interface The DS26518 provides a versatile backplane interface that can be configured to: * Transmit and receive two-frame elastic stores * Mapping of T1 channels into a 2.048MHz backplane * IBO mode for multiple framers to share the backplane signals * Transmit and receive channel blocking capability * Fractional T1/E1/J1 support * Hardware-based (through the backplane interface) or processor-based signaling * Flexible backplane clock providing frequencies of 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz * Backplane clock and frame pulse (TSSYNCIOn) generator 9.8.1 Elastic Stores The DS26518 contains dual, two-frame elastic stores for each framer: one for the receive direction and one for the transmit direction. Both elastic stores are fully independent. The transmit- and receive-side elastic stores can be enabled/disabled independently of each other. Also, the transmit or receive elastic store can interface to either a 1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate for the other elastic store. All eight channels have their own TSYSCLKn/RSYSCLKn pins, allowing a unique backplane system clock for each channel. This allows for maximum flexibility in the design of the backplane clock structure. The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26518 is in the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode the elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Second, they can be used to absorb the differences in phase and frequency between the T1 or E1 clock and an asynchronous (i.e., not locked) backplane clock, which can be 1.544MHz or 2.048MHz. If the two clocks are not frequency locked, the elastic stores manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the network and the backplane. If the elastic store is enabled while in E1 mode, then either CAS or CRC4 multiframe boundaries are indicated via the RMSYNCn output as controlled by the RSMS2 control bit (RIOCR.1). If the user selects to apply a 1.544MHz clock to the RSYSCLKn pin, the Receive Blank Channel Select Registers (RBCS1-4) determine which channels of the received E1 data stream will be deleted. In this mode an F-bit location is inserted into the RSERn data and set to one. Also, in 1.544MHz applications, the RCHBLKn output will not be active in channels 25 to 32 (or in other words, RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data will be repeated at RSERn and the RLS4.5 and RLS4.6 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the RLS4.5 and RLS4.7 bits will be set to a one. The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the Interleave Bus Option (IBO), which is discussed in Section 9.8.2. Table 9-3 shows the registers related to the elastic stores. Table 9-3. Registers Related to the Elastic Store REGISTER Receive I/O Configuration Register (RIOCR) Receive Elastic Store Control Register (RESCR) Receive Latched Status Register 4 (RLS4) Receive Interrupt Mask Register 4(RIM4) Transmit Elastic Store Control Register (TESCR) Transmit Latched Status Register 1 (TLS1) Transmit Interrupt Mask Register 1 (TIM1) FRAMER 1 ADDRESSES 084h 085h 093h 0A3h 185h 190h 1A0h FUNCTION Sync and clock selection for the receiver. Receive elastic store control. Receive elastic store empty full status. Receive interrupt mask for elastic store. Transmit elastic control such as minimum mode. Transmit elastic store latched status. Transmit elastic store interrupt mask. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. 36 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.8.1.1 Elastic Stores Initialization There are two elastic store initializations that may be used to improve performance in certain applications: elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store's read and write pointers and are useful primarily in synchronous applications (RSYSCLKn/TSYSCLKn are locked to RCLKn/TCLKn, respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align bit is used to center the read/write pointers to the extent possible. Table 9-4. Elastic Store Delay After Initialization INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align N = 9 for RSZS = 0; N = 2 for RSZS = 1 REGISTER BIT RESCR.2 TESCR.2 RESCR.3 TESCR.3 DELAY N bytes < Delay < 1 Frame + N bytes N bytes < Delay < 1 Frame + N bytes 1/2 Frame < Delay < 1 1/2 Frames 1/2 Frame < Delay < 1 1/2 Frames 9.8.1.2 Minimum Delay Mode Elastic store minimum delay mode may be used when the elastic store's system clock is locked to its network clock (i.e., RCLKn locked to RSYSCLKn for the receive side and TCLKn locked to TSYSCLKn for the transmit side). RESCR.1 enables the receive elastic store minimum delay mode. When enabled, the elastic stores will be forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the restriction mentioned above, RSYNCn must be configured as an output when the receive elastic store is in minimum delay mode, and TSYNCn must be configured as an output when transmit minimum delay mode is enabled. In this mode, the SYNC outputs are always in frame mode (multiframe outputs are not allowed). In a typical application RSYSCLKn and TSYSCLKn are locked to RCLKn, and RSYNCn (frame output mode) is connected to TSSYNCIOn (frame input mode). The slip zone select bit (RSZS at RESCR.4) must be set to 1. All the slip contention logic in the framer is disabled (since slips cannot occur). On power-up after the RSYSCLKn and TSYSCLKn signals have locked to their respective network clock signals, the elastic store reset bit (RESCR.2) should be toggled from a zero to a one to ensure proper operation. 9.8.1.3 Additional Receive Elastic Store Information If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLKn pin. See Section 9.8.2 for higher rate system clock applications. The user has the option of either providing a frame/multiframe sync at the RSYNCn pin or having the RSYNCn pin provide a pulse on frame/multiframe boundaries. If signaling reinsertion is enabled, the robbed-bit signaling data is realigned to the multiframe sync input on RSYNCn. Otherwise, a multiframe sync input on RSYNCn is treated as a simple frame boundary by the elastic store. The framer will always indicate frame boundaries on the network side of the elastic store via the RFSYNCn output whether the elastic store is enabled or not. Multiframe boundaries will always be indicated via the RMSYNCn output. If the elastic store is enabled, then RMSYNCn will output the multiframe boundary on the backplane side of the elastic store. When the device is receiving T1 and the backplane is enabled for 2.048MHz operation, the RMSYNCn signal will output the T1 multiframe boundaries as delayed through the elastic store. When the device is receiving E1 and the backplane is enabled for 1.544MHz operation, the RMSYNCn signal will output the E1 multiframe boundaries as delayed through the elastic store. If the user selects to apply a 2.048MHz clock to the RSYSCLKn pin, the user can use the backplane blank channel select registers (RBCS1-4) to determine which channels will have the data output at RSERn forced to all ones. 37 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane Setting the TSCLKM bit in TIOCR.4 enables the transmit elastic store to operate with a 2.048MHz backplane (32 time slots / frame). In this mode the user can choose which of the backplane channels on TSERn will be mapped into the T1 data stream by programming the Transmit Blank Channel Select registers (TBCS1-4). A logic 1 in the associated bit location forces the transmit elastic store to ignore backplane data for that channel. Typically the user will want to program eight channels to be ignored. The default (power-up) configuration will ignore channels 25-32, so that the first 24 backplane channels are mapped into the T1 transmit data stream. For example, if the user desired to transmit data from the 2.048MHz backplane channels 2-16 and 18-26, the TBCS registers should be programmed as follows: TBCS1 = 01h :: ignore backplane channel 1 :: TBCS2 = 00h TBCS3 = 01h :: ignore backplane channel 17 :: TBCS4= FCh :: ignore backplane channels 27-32 :: 9.8.1.5 Mapping T1 Channels onto a 2.048MHz Backplane Setting the RSCLKM bit in RIOCR.4 will enable the receive elastic store to operate with a 2.048MHz backplane (32 time slots/frame). In this mode the user can choose which of the backplane channels on RSERn receive the T1 data by programming the Receive Blank Channel Select registers (RBCS1-4). A logic 1 in the associated bit location will force RSERn high for that backplane channel. Typically the user will want to program eight channels to be blanked. The default (power-up) configuration will blank channels 25 to 32, so that the 24 T1 channels are mapped into the first 24 channels of the 2.048MHz backplane. If the user chooses to blank channel 1 (TS0) by setting RBCS1.0 = 1, then the F-bit will be passed into the MSB of TS0 on RSERn. For example, if: RBCS1 = 01h RBCS2 = 00h RBCS3 = 01h RBCS4 = FCh Then on RSERn: Channel 1 (MSB) = F-bit Channel 1 (bits 1-7) = all ones Channels 2-16 = T1 channels 1-15 Channel 17 = all ones Channels 18-26 = T1 channels 16-24 Channels 27-32 = all ones Note that when two or more sequential channels are chosen to be blanked, the receive slip zone select bit should be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), the RSZS bit can be set to one, which can provide a lower occurrence of slips in certain applications. If the two-frame elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data will be repeated at RSERn and the RLS4.5 and RLS4.6 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the RLS4.5 and RLS4.7 bits will be set to a one. 9.8.1.6 Receiving Mapped E1 Transmit Channels from a 1.544MHz Backplane The user can use the TSCLKM bit in TIOCR.4 to enable the transmit elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will have allones data inserted by programming the Transmit Blank Channel Select registers (TBCS1-4). A logic 1 in the associated bit location will cause the elastic store to force all ones at the outgoing E1 data for that channel. Typically the user will want to program eight channels to be blanked. The default (power-up) configuration will blank channels 25 to 32, so that the first 24 E1 channels are mapped from the 24 channels of the 1.544MHz backplane. 38 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane The user can use the RSCLKM bit in RIOCR.4 to enable the receive elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will be ignored (not transmitted onto RSERn) by programming the Receive Blank Channel Select registers (RBCS1-4). A logic 1 in the associated bit location will cause the elastic store to ignore the incoming E1 data for that channel. Typically, the user will want to program eight channels to be ignored. The default (power-up) configuration will ignore channels 25 to 32, so that the first 24 E1 channels are mapped into the 24 channels of the 1.544MHz backplane. In this mode the F-bit location at RSERn is always set to 1. For example, if the user wants to ignore E1 time slots 0 (channel 1) and TS 16 (channel 17), the RBCS registers would be programmed as follows: RBCS1 = 01h RBCS2 = 00h RBCS3 = 01h RBCS4 = FCh 9.8.2 IBO Multiplexing The DS26518 offers two methods of multiplexing data streams onto a high-speed backplane bus. The traditional method of IBO operation that allows the user to gang signals together on the PCB is supported. RSERn and RSIGn will tri-state at the appropriate times to allow the ganging of these signals together. The default method multiplexes the data streams internally and then outputs them on one pin, i.e., RSER1. For example, if the user wants to multiplex RSER[1:8] together to make a 16MHz high-speed bus, the data stream will be output on RSER1 only. The selection between external ganging and internal multiplexing is made via GTCR1.GIBO. Note that in IBO mode, the channel block signals TCHBLKn and RCHBLKn are referenced to as TSYSCLKn and RSYSCLKn. Figure 9-11, Figure 9-12, and Figure 9-13 show the equivalent internal circuit for each IBO mode. These figures only show channels 1-8. Table 9-5 describes the pin function changes for each mode of the IBO multiplexer. Table 9-5. Registers Related to the IBO Multiplexer REGISTER Global Transceiver Control Register 1 (GTCR1) Global Framer Control Register 1 (GFCR1) Receive Interleave Bus Operation Control Register (RIBOC) Transmit Interleave Bus Operation Control Register (TIBOC) FRAMER 1 ADDRESSES 00F0h 00F1h FUNCTION This is a global register used to specify ganged operation for the IBO. This global register defines the number of devices per bus and bus speed. This register configures the per-port IBO enable and type of interleaving (channel vs. frame). This register configures the per-port IBO enable and type of interleaving (channel vs. frame). 088h 188h Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. 39 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-11. IBO Multiplexer Equivalent Circuit--4.096MHz RSER1 RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSIG1 Port # 1 Backplane Interface RSYNC1 RSYSCLK1 TSER1 TSIG1 TSSYNCIO1 TSYSCLK1 Port # 2 Backplane Interface RSER3 RSIG3 Port # 3 Backplane Interface RSYNC3 RSYSCLK3 TSER3 TSIG3 TSSYNCIO3 TSYSCLK3 Port # 4 Backplane Interface RSER5 RSIG5 Port # 5 Backplane Interface RSYNC5 RSYSCLK5 TSER5 TSIG5 TSSYNCIO5 TSYSCLK5 Port # 6 Backplane Interface RSER7 RSIG7 Port # 7 Backplane Interface RSYNC7 RSYSCLK7 TSER7 TSIG7 TSSYNCIO7 TSYSCLK7 Port # 8 Backplane Interface 40 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-12. IBO Multiplexer Equivalent Circuit--8.192MHz RSER1 RSIG1 RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSSYNC TSYSCLK TSER TSIG Port # 1 Backplane Interface RSYNC1 RSYSCLK1 TSER1 TSIG1 TSSYNCIO1 TSYSCLK1 Port # 2 Backplane Interface Port # 3 Backplane Interface Port # 4 Backplane Interface RSER5 RSIG5 RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK Port # 5 Backplane Interface RSYNC5 RSYSCLK5 TSER5 TSIG5 TSSYNCIO5 TSYSCLK5 Port # 6 Backplane Interface Port # 7 Backplane Interface Port # 8 Backplane Interface 41 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-13. IBO Multiplexer Equivalent Circuit--16.384MHz RSER(1) RSER(2) RSER(3) RSER(4) RSER(5) RSER(6) RSER(7) RSER(8) RIBO_OEB(1-8) RSER1 RSIG(1) RSIG(2) RSIG(3) RSIG(4) RSIG(5) RSIG(6) RSIG(7) RSIG(8) RIBO_OEB(1-8) RSIG1 Port # 1 Backplane Interface RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK To Mux RSYNC1 RSYSCLK1 TSER1 TSIG1 TSSYNCIO1 TSYSCLK1 To Mux Port # 2 Backplane Interface To Mux Port # 3 Backplane Interface To Mux Port # 4 Backplane Interface To Mux Port # 5 Backplane Interface To Mux Port # 6 Backplane Interface To Mux Port # 7 Backplane Interface To Mux Port # 8 Backplane Interface 42 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 9-6. RSERn Output Pin Definitions (GTCR1.GIBO = 0) PIN RSER1 NORMAL USE Receive Serial Data for Port 1 Receive Serial Data for Port 2 Receive Serial Data for Port 3 Receive Serial Data for Port 4 Receive Serial Data for Port 5 Receive Serial Data for Port 6 Receive Serial Data for Port 7 Receive Serial Data for Port 8 4.096MHz IBO Combined Receive Serial Data for Ports 1 and 2 Reserved Combined Receive Serial Data for Ports 3 and 4 Unused Combined Receive Serial Data for Ports 5 and 6 Unused Combined Receive Serial Data for Ports 7 and 8 Unused 8.192MHz IBO Combined Receive Serial Data for Ports 1-4 Unused 16.384MHz IBO Receive Serial Data for Ports 1-8 Unused RSER2 RSER3 Unused Unused RSER4 Unused Combined Receive Serial Data for Ports 5-8 Unused Unused RSER5 Unused RSER6 Unused RSER7 Unused Unused RSER8 Unused Unused Table 9-7. RSIGn Output Pin Definitions (GTCR1.GIBO = 0) PIN RSIG1 NORMAL USE Receive Signaling Data for Port 1 Receive Signaling Data for Port 2 Receive Signaling Data for Port 3 Receive Signaling Data for Port 4 Receive Signaling Data for Port 5 Receive Signaling Data for Port 6 Receive Signaling Data for Port 7 Receive Signaling Data for Port 8 4.096MHz IBO Combined Receive Signaling Data for Ports 1 and 2 Unused Combined Receive Signaling Data for Ports 3 and 4 Unused Combined Receive Signaling Data for Ports 5 and 6 Unused Combined Receive Signaling Data for Ports 7 and 8 Unused 8.192MHz IBO Combined Receive Signaling Data for Ports 1-4 Unused 16.384MHz IBO Receive Signaling Data for Ports 1-8 Unused RSIG2 RSIG3 Unused Unused RSIG4 Unused Combined Receive Signaling Data for Ports 5-8 Unused Unused RSIG5 Unused RSIG6 Unused RSIG7 Unused Unused RSIG8 Unused Unused 43 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 9-8. TSERn Input Pin Definitions (GTCR1.GIBO = 0) PIN TSER1 NORMAL USE Transmit Serial Data for Port 1 Transmit Serial Data for Port 2 Transmit Serial Data for Port 3 Transmit Serial Data for Port 4 Transmit Serial Data for Port 5 Transmit Serial Data for Port 6 Transmit Serial Data for Port 7 Transmit Serial Data for Port 8 4.096MHz IBO Combined Transmit Serial Data for Ports 1 and 2 Unused Combined Transmit Serial Data for Ports 3 and 4 Unused Combined Transmit Serial Data for Ports 5 and 6 Unused Combined Transmit Serial Data for Ports 7 and 8 Unused 8.192MHz IBO Combined Transmit Serial Data for Ports 1-4 Unused 16.384MHz IBO Transmit Serial Data for Ports 1-8 Unused TSER2 TSER3 Unused Unused TSER4 Unused Combined Transmit Serial Data for Ports 5-8 Unused Unused TSER5 Unused TSER6 Unused TSER7 Unused Unused TSER8 Unused Unused Table 9-9. TSIGn Input Pin Definitions (GTCR1.GIBO = 0) PIN TSIG1 NORMAL USE Transmit Signaling Data for Port 1 Transmit Signaling Data for Port 2 Transmit Signaling Data for Port 3 Transmit Signaling Data for Port 4 Transmit Signaling Data for Port 5 Transmit Signaling Data for Port 6 Transmit Signaling Data for Port 7 Transmit Signaling Data for Port 8 4.096MHz IBO Combined Transmit Signaling Data for Ports 1 and 2 Unused Combined Transmit Signaling Data for Ports 3 and 4 Unused Combined Transmit Signaling Data for Ports 5 and 6 Unused Combined Transmit Signaling Data for Ports 7 and 8 Unused 8.192MHz IBO Combined Transmit Signaling Data for Ports 1-4 Unused 16.384MHz IBO Transmit Signaling Data for Ports 1-8 Unused TSIG2 TSIG3 Unused Unused TSIG4 Unused Combined Transmit Signaling Data for Ports 5-8 Unused Unused TSIG5 Unused TSIG6 Unused TSIG7 Unused Unused TSIG8 Unused Unused 44 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 9-10. RSYNCn Input Pin Definitions (GTCR1.GIBO = 0) PIN RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYNC5 RSYNC6 RSYNC7 RSYNC8 NORMAL USE Receive Frame Pulse for Port 1 Receive Frame Pulse for Port 2 Receive Frame Pulse for Port 3 Receive Frame Pulse for Port 4 Receive Frame Pulse for Port 5 Receive Frame Pulse for Port 6 Receive Frame Pulse for Port 7 Receive Frame Pulse for Port 8 4.096MHz IBO Receive Frame Pulse for Ports 1 and 2 Unused Receive Frame Pulse for Ports 3 and 4 Unused Receive Frame Pulse for Ports 5 and 6 Unused Receive Frame Pulse for Ports 7 and 8 Unused 8.192MHz IBO Receive Frame Pulse for Ports 1-4 Unused Unused Unused Receive Frame Pulse for Ports 5-8 Unused Unused Unused 16.384MHz IBO Receive Frame Pulse for Ports 1-8 Unused Unused Unused Unused Unused Unused Unused 9.8.3 H.100 (CT Bus) Compatibility The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN (RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26518 to accept a CT-buscompatible frame-sync signal (CT_FRAME) at the RSYNCn and TSSYNCIOn (input mode) inputs. See Figure 9-14 and Figure 9-15. The following rules apply to the H100EN control bit: 1) The H100EN bit controls the sampling point for the RSYNCn (input mode) and TSSYNCIOn (input mode) only. The RSYNCn output and other sync signals are not affected. 2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store buffers. 3) The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with 4.096MHz IBO mode or 2.048MHz backplane operation. 4) The H100EN bit in RIOCR controls both RSYNCn and TSSYNCIOn (i.e., there is no separate control bit for the TSSYNCIOn). 5) The H100EN bit does not invert the expected signal; RSYNCINV (RIOCR) and TSSYNCINV (TIOCR) must be set high to invert the inbound sync signals. 45 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode RSYNCn1 RSYNCn2 RSYSCLKn RSERn BIT 8 BIT 1 tBC 3 BIT 2 NOTE 1: RSYNCn INPUT MODE IN NORMAL OPERATION. NOTE 2: RSYNCn INPUT MODE, H100EN = 1 AND RSYNCINV = 1. NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns or 488ns ALSO ACCEPTABLE. Figure 9-15. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode TSSYNCIOn1 TSSYNCIOn2 TSYSCLKn TSERn BIT 8 BIT 1 tBC3 BIT 2 NOTE 1: TSSYNCIOn IN NORMAL OPERATION. NOTE 2: TSSYNCIOn WITH H100EN = 1 and TSSYNCINV = 1. NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns OR 488ns ALSO ACCEPTABLE. 46 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.8.4 Transmit and Receive Channel Blocking Registers The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLKn and TCHBLKn pins, respectively. The RCHBLKn and TCHBLKn pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to a one, the RCHBLKn and TCHBLKn pins will be held high during the entire corresponding channel time. When used with a T1 (1.544MHz) backplane, only TCBR1 to TCBR3 will be used. TCBR4 is included to support an E1 (2.048MHz) backplane when the elastic store is configured for T1-to-E1 rate conversion (See Section 9.8.1). 9.8.5 Transmit Fractional Support (Gapped Clock Mode) The DS26518 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled via the Transmit Gapped Clock Channel Select Registers (TGCCS1-4). The transmit path is enabled for gapped clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the channel is omitted (only the seven most significant bits of the channel have clocks). 9.8.6 Receive Fractional Support (Gapped Clock Mode) The DS26518 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the RCHCLKn signal. The channel selection is controlled via the Receive Gapped Clock Channel Select Registers (RGCCS1-4). The receive path is enabled for gapped clock mode with the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the channel is omitted (only the seven most significant bits of the channel have clocks). 47 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9 Framers The DS26518 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, T1 FDL data, and E1 Si- and Sa-bit information. The receive-side framer decodes AMI, B8ZS line coding, synchronizes to the data stream, reports alarm information, counts framing/coding and CRC errors, and provides clock/data and frame-sync signals to the backplane interface section. Diagnostic capabilities include loopbacks, and 16-bit loop-up and loop-down code detection. The device contains a set of internal registers for host access and control of the device. On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS (zero code suppression) and AMI line coding. Both the transmit and receive path have an HDLC controller. The HDLC controller transmits and receives data via the framer block. The HDLC controller may be assigned to any time slot, portion of a time slot, or to FDL (T1). The HDLC controller has separate 64-byte Tx and Rx FIFO to reduce the amount of processor overhead required to manage the flow of data. The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An IBO (Interleave Bus Option) is provided to allow multiple framers in the DS26518 to share a high-speed backplane. 9.9.1 T1 Framing DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit, the F-bit. The F-bit contains a fixed pattern for the receiver to delineate the frame boundaries. The F-bit is inserted once per frame at the beginning of the transmit frame boundary. The frames are further grouped into bundles of frames 12 for D4 and 24 for ESF. The D4 and ESF framing modes are outlined in Table 9-11 and Table 9-12. In the D4 mode, framing bit for frame 12 is ignored if Japanese Yellow is selected. Table 9-13 shows SLC-96 framing. Table 9-11. D4 Framing Mode FRAME NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 Ft 1 0 0 0 1 1 0 1 1 1 0 0 B A Fs SIGNALING 48 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 9-12. ESF Framing Mode FRAME NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FRAMING FDL CRC1 0 CRC2 0 CRC3 CRC4 0 CRC5 1 CRC6 1 CRC SIGNALING Table 9-13. SLC-96 Framing FRAME NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Ft 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 C1 (Concentrator Bit) 1 C2 (Concentrator Bit) 0 D C B A Fs 0 SIGNALING 49 of 286 DS26518 8-Port T1/E1/J1 Transceiver FRAME NUMBER 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ft 1 C4 (Concentrator Bit) 0 C5 (Concentrator Bit) 1 C6 (Concentrator Bit) 0 C7 (Concentrator Bit) 1 C8 (Concentrator Bit) 0 C9 (Concentrator Bit) 1 C10 (Concentrator Bit) 0 C11 (Concentrator Bit) 1 0 (Spoiler Bit) 0 1 (Spoiler Bit) 1 0 (Spoiler Bit) 0 M1 (Maintenance Bit) 1 M2 (Maintenance Bit) 0 M3 (Maintenance Bit) 1 A1 (Alarm Bit) 0 A2 (Alarm Bit) 1 S1 (Switch Bit) 0 S2 (Switch Bit) 1 S3 (Switch Bit) 0 S4 (Switch Bit) 1 1 (Spoiler Bit) 0 0 D C B A D C B A Fs C3 (Concentrator Bit) SIGNALING 50 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.2 E1 Framing The E1 framing consists of FAS, NFAS detection as shown in Table 9-14. Table 9-14. E1 FAS/NFAS Framing CRC-4 FRAME # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TYPE FAS NFAS FAS NFAS FAS NFAS FAS NFAS FAS NFAS FAS NFAS FAS NFAS FAS NFAS 1 C1 0 C2 0 C3 1 C4 0 C1 1 C2 1 C3 E1 C4 E2 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A 4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 C = C bits are the CRC-4 remainder; A = alarm bits; Sa = bits for data link. 51 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 9-15 shows the registers that are related to setting up the framing. Table 9-15. Registers Related to Setting Up the Framer REGISTER Transmit Master Mode Register (TMMR) Transmit Control Register 1 (TCR1) Transmit Control Register 2 (T1.TCR2) Transmit Control Register 3 (TCR3) Receive Master Mode Register (RMMR) Receive Control Register 1 (RCR1) Receive Control Register 2 (T1RCR2) Receive Control Register 2 (E1RCR2) Receive Latched Status Register 1 (RLS1) Receive Interrupt Mask Register 1 (RIM1) Receive Latched Status Register 2 (RLS2) Receive Interrupt Mask Register 2 (RIM2) Receive Latched Status Register 4 (RLS4) Receive Interrupt Mask Register 4 (RIM4) Frames Out of Sync Count Register 1 (FOSCR1) Frames Out of Sync Count Register 2 (FOSCR2) E1 Receive Align Frame Register (E1RAF) E1 Receive Non-Align Frame Register (E1RNAF) Transmit SLC-96 Data Link Register 1 (T1TSLC1) Transmit SLC-96 Data Link Register 2 (T1TSLC2) Transmit SLC-96 Data Link Register 3 (T1TSLC3) Receive SLC-96 Data Link Register 1 (T1RSLC1) Receive SLC-96 Data Link Register 2 (T1RSLC2) Receive SLC-96 Data Link Register 3 (T1RSLC3) FRAMER 1 ADDRESSES 180h 181h 182h 183h 080h 081h 014h 082h 090h 0A0h 091h 0A1h 093h 0A3h 054h 055h 064h 065h 164h 165h 166h 064h 065h 066h T1/E1 mode. Source of the F-bit. F-bit corruption, selection of SLC-96. ESF or D4 mode selection. T1/E1 selection for receiver. Resynchronization criteria for the framer. T1 remote alarm and OOF criteria. E1 receive loss of signal criteria selection. Receive latched status 1. Receive interrupt mask 1. Receive latched status 2. Receive interrupt mask 2. Receive latched status 4. Receive interrupt mask 4. Framer out of sync register 1. Framer out of sync register 2. RAF byte. RNAF byte. Transmit SLC-96 bits. Transmit SLC-96 bits. Transmit SLC-96 bits. Receive SLC-96 bits. Receive SLC-96 bits. Receive SLC-96 bits. FUNCTION Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8. 52 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.3 T1 Transmit Synchronizer The DS26518 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSERn. The TFM (TCR3.2) control bit determines whether the transmit synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are located in the TSYNCC register. The latched status bit TLS3.0 (LOFD) is provided to indicate that a loss of frame synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INTB. Note that when the transmit synchronizer is used, the TSYNCn signal should be set as an output (TSIO = 1) and the recovered frame-sync pulse will be output on this signal. The recovered CRC-4 multi-frame sync pulse will be output if enabled with TIOCR.0 (TSM = 1). Other key points concerning the E1 transmit synchronizer: 1) The Tx synchronizer is not operational when the transmit elastic store is enabled, including IBO modes. 2) The Tx synchronizer does not perform CRC-6 alignment verification (ESF mode) and does not verify CRC-4 codewords. The Tx synchronizer cannot search for the CAS multiframe. Table 9-16 shows the registers related to the transmit synchronizer. Table 9-16. Registers Related to the Transmit Synchronizer REGISTER Transmit Synchronizer Control Register (TSYNCC) Transmit Control Register 3 (TCR3) Transmit Latched Status Register 3 (TLS3) Transmit Interrupt Mask Register 3 (TIM3) Transmit I/O Configuration Register (TIOCR) FRAMER 1 ADDRESSES 18Eh 183h 192h 1A2h 184h FUNCTION Resynchronization control for the transmit synchronizer. TFM bit selects between D4 and ESF for the transmit synchronizer. Provides latched status for the transmit synchronizer. Provides mask bits for the TLS3 status. TSYNCn should be set as an output. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8. 53 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.4 Signaling The DS26518 supports both software and hardware-based signaling. Interrupts can be generated on changes of signaling data. The DS26518 is also equipped with receive-signaling freeze on loss of synchronization (OOF), carrier loss or change of frame alignment. The DS26518 also has hardware pins to indicate signaling freeze. Features include the following: Flexible signaling support: Software or hardware based Interrupt generated on change of signaling data Receive-signaling freeze on loss of frame, loss of signal, or change of frame alignment Hardware pins for carrier loss and signaling freeze indication Table 9-17. Registers Related to Signaling REGISTER Transmit-Signaling Registers 1 to 16 (TS1 to TS16) Software-Signaling Insertion Enable Registers 1 to 4 (SSIE1 to SSIE4) Transmit Hardware-Signaling Channel Select Registers 1 to 4 (THSCS1 to THSCS4) Receive-Signaling Control Register (RSIGC) Receive-Signaling All-Ones Insertion Registers 1 to 3 (T1RSAOI1 to T1RSAOI3) Receive-Signaling Registers 1 to 16 (RS1 to RS16) Receive-Signaling Status Registers 1 to 4 (RSS1 to RSS4) Receive-Signaling Change of State Enable Registers 1 to 4 (RSCSE1 to RSCSE4) Receive Latched Status Register 4 (RLS4) Receive Interrupt Mask Register 4 (RIM4) Receive-Signaling Reinsertion Enable Registers 1 to 4 (RSI1 to RSI4) FRAMER 1 ADDRESSES 140h to 14Bh (T1/J1) 140h to 14Fh (E1 CAS) 118h, 119h, 11Ah, 11Bh 1C8h, 1C9h, 1CAh, 1CBh FUNCTION Transmit ABCD signaling. When enabled, signaling is inserted for the channel. Bits determine which channels will have signaling inserted in hardware-signaling mode. Freeze control for receive signaling. Registers for all-ones insertion (T1 mode only). Receive-signaling bytes. Receive-signaling change of status bits. Receive-signaling change of state interrupt enable. Receive-signaling change of state bit. Receive-signaling change of state interrupt mask bit. Registers for signaling reinsertion. 013h 038h, 039h, 03Ah 040h to 04Bh (T1/J1) 040h to 04Fh (E1) 098h to 09Ah (T1/J1) 98h to 9Fh (E1) 0A8h, 0A9h, 0AAh, 0ABh 093h 0A3h 0C8h, 0C9h, 0CAh, 0CBh Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8. 54 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.4.1 Transmit-Signaling Operation There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit signaling registers, TS1-TS16, while hardware based refers to using the TSIGn pins. Both methods can be used simultaneously. 9.9.4.1.1 Processor-Based Transmit Signaling In processor-based mode, signaling data is loaded into the transmit-signaling registers (TS1-TS16) via the host interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. The user can utilize the transmit multiframe interrupt in the Transmit Latched Status Register 1 (TLS1.2) to know when to update the signaling bits. The user need not update any transmit signaling register for which there is no change of state for that register. Each transmit-signaling register contains the robbed-bit signaling (TCR1.4 in T1 mode) or TS16 CAS signaling (TCR1.6 in E1 mode) for one time slot that will be inserted into the outgoing stream. Signaling data can be sourced from the TS registers on a per-channel basis by using the Software Signaling Insertion Enable Registers, SSIE1-4. In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1-TS12 contain a full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1 D4 framing mode, the framer uses A and B bit positions for the next multiframe. The C and D bit positions become `don't care' in D4 mode. In E1 mode, TS16 carries the signaling information. This information can be in either CCS (Common Channel Signaling) or CAS (Channel Associated Signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In "channel" numbering, TS0-TS31 are labeled channels 1 through 32. In "Phone Channel" numbering TS1-TS15 are labeled channel 1 to channel 15 and TS17-TS31 are labeled channel 15 to channel 30. 9.9.4.1.2 Time Slot Numbering Schemes TS Channel Phone Channel 0 1 1 2 1 2 3 2 3 4 3 4 5 4 5 6 5 6 7 6 7 8 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 9.9.4.1.3 Hardware-Based Transmit Signaling In hardware-based mode, signaling data is input via the TSIGn pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSERn pin. Signaling data may be input via the Transmit Hardware-Signaling Channel Select Register (THSCS1) function. The framer can be set up to take the signaling data presented at the TSIGn pin and insert the signaling data into the PCM data stream that is being input at the TSERn pin. The user can control which channels are to have signaling data from the TSIGn pin inserted into them on a per-channel basis. The signaling insertion capabilities of the framer are available whether the transmit-side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLKn) can be either 1.544MHz or 2.048MHz. 55 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.4.2 Receive-Signaling Operation There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit- and receive-signaling registers, RS1-RS16. Hardware based refers to the RSIGn pin. Both methods can be used simultaneously. 9.9.4.2.1 Processor-Based Receive Signaling Signaling information is sampled from the receive data stream and copied into the Receive-Signaling Registers, RS1-RS16. The signaling information in these registers is always updated on multiframe boundaries. This function is always enabled. 9.9.4.2.2 Change of State To avoid constant monitoring of the receive-signaling registers, the DS26518 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. RSCSE1-4 are used to select which channels can cause a change of state indication. The change of state is indicated in Receive Latched Status Register 4 (RLS4.3). If signaling integration is enabled, the new signaling state must be constant for three multiframes before a change of state indication is indicated. The user can enable the INTB pin to toggle low upon detection of a change in signaling by setting the interrupt mask bit RIM4.3. The signaling integration mode is global and cannot be enabled on a channel-by-channel basis. The user can identity which channels have undergone a signaling change of state by reading the ReceiveSignaling Status Registers (RSS1-4) . The information from these registers will tell the user which RSx register to read for the new signaling data. All changes are indicated in the RSS1-4 registers regardless of the RSCSE1-4 registers. 9.9.4.2.3 Hardware-Based Receive Signaling In hardware-based signaling the signaling data is can be obtained from the RSERn pin or the RSIGn pin. RSIGn is a signaling PCM stream output on a channel by channel basis from the signaling buffer. The T1 robbed bit or E1 TS16 signaling data is still present in the original data stream at RSERn. The signaling buffer provides signaling data to the RSIGn pin and also allows signaling data to be reinserted into the original data stream in a different alignment that is determined by a multiframe signal from the RSYNCn pin. In this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLKn) can be either 1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIGn in the lower nibble of each channel. The RSIGn data is updated once a multiframe (3ms for T1 ESF, 1.5ms for T1 D4, 2ms for E1 CAS) unless a signaling freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIGn in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each channel. 9.9.4.2.4 Receive-Signaling Reinsertion at RSERn In this mode, the user will provide a multiframe sync at the RSYNCn pin and the signaling data will be reinserted based on this alignment. In T1 mode, this results in two copies of the signaling data in the RSERn data stream. The original signaling data based on the Fs/ESF frame positions and the realigned data based on the user supplied multiframe sync applied at RSYNCn. In voice channels this extra copy of signaling data is of little consequence. Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion, the elastic store must be enabled and for T1, the backplane clock can be either 1.544MHz or 2.048MHz. E1 signaling information cannot be reinserted into a 1.544MHz backplane. Signaling reinsertion mode is enabled, on a per-channel basis by setting the receive-signaling reinsertion channel select bit high in the RSI1-4 register. The channels that are to have signaling reinserted are selected by writing to the RSI1-4 registers. In E1 mode, the user will generally select all channels or none for reinsertion. 9.9.4.2.5 Force Receive-Signaling All Ones In T1 mode, the user can on a per-channel basis force the robbed-bit signaling bit positions to a one. This is done by using the Receive-Signaling All-Ones Insertion Registers (T1RSAOI1-3). The user sets the channel select bit in the T1RSAOI1-3 registers to select the channels that are to have the signaling forced to one. 56 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.4.2.6 Receive-Signaling Freeze The signaling data in the four multiframe signaling buffers will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or change of frame alignment. In T1 mode, this action meets the requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four multiframe buffer provides a three multiframe delay in the signaling bits provided at the RSIGn pin (and at the RSERn pin if receivesignaling reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data will be held in the last known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data will be held in the old state for at least an additional 9ms (4.5ms in D4 framing mode, 6ms for E1 mode) before being allowed to be updated with new signaling data. The receive-signaling registers are frozen and not updated during a loss of sync condition. They will contain the most recent signaling information before the LOF occurred. 9.9.4.3 Transmit SLC-96 Operation (T1 Mode Only) In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into alarm, maintenance, spoiler, and concentrator bits as well as 12-bits of the normal Fs pattern. Additional SLC-96 information can be found in BellCore document TR-TSY-000008. Registers related to the transmit FDL are shown in Table 9-18. Table 9-18. Registers Related to SLC-96 REGISTER Transmit FDL Register (T1TFDL) Transmit SLC-96 Data Link Registers 1 to 3 (T1TSLC1:T1TSLC3) Transmit Control Register 2 T1.TCR2) Transmit Latched Status Register 1 (TLS1) Receive SLC-96 Data Link Registers 1 to 3 (T1RSLC1:T1RSLC3) Receive Latched Status Register 7 (RLS7) FRAMER 1 ADDRESSES 162h 164h, 165h, 166h 182h 190h 064h, 065h, 066h 096h FUNCTION For sending messages in transmit SLC-96 Ft/Fs bits. Registers that control the SLC-96 overhead values. Transmit control for data selection source for the Ft/Fs bits. Status bit for indicating transmission of data link buffer. -- Receive SLC-96 alignment event. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. The T1TFDL register is used to insert the SLC-96 message fields. To insert the SLC-96 message using the T1TFDL register, the user should configure the DS26518 as shown below: * T1.TCR2.6 (TSLC96) = 1 Enable Transmit SLC-96. Source FS bits via TFDL or SLC-96 formatter. * T1.TCR2.7 (TFDLS) = 0 D4 framing mode. * TCR3.2 (TFM) = 1 Do not "pass through" TSERn F-bits. * TCR1.6 (TFPT) = 0 The DS26518 will automatically insert the 12-bit alignment pattern in the Fs bits for the SLC-96 data link frame. Data from the T1TSLC1-3 will be inserted into the remaining Fs-bit locations of the SLC-96 multiframe. The status bit TSLC96 located at TLS1.4 will set to indicate that the SLC-96 data link buffer has been transmitted and that the user should write new message data into T1TSLC1-3. The host will have 9ms after the assertion of TLS1.4 to write the registers T1TSLC1-3. If no new data is provided in these registers, the previous values will be retransmitted. 57 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.4.4 Receive SLC-96 Operation (T1 Mode Only) In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36-bits are divided into alarm, maintenance, spoiler, and concentrator bits as well as 12-bits of the normal Fs pattern. Additional SLC-96 information can be found in BellCore document TR-TSY-000008. To enable the DS26518 to synchronize onto a SLC-96 pattern, the following configuration should be used: * RCR1.5 (RFM) = 1 Set to D4 framing mode. Set to cross-couple Ft and Fs bits. * RCR1.3 (SYNCC) = 1 * T1RCR2.4 (RSLC96) = 1 Enable SLC-96 synchronizer. Set to minimum sync time. * RCR1.7 (SYNCT) = 0 The SLC-96 message bits can be extracted via the T1RSLC1-3 registers. The status bit RSLC96 located at RLS7.3 is useful for retrieving SLC-96 message data. The RSLC96 bit will indicate when the framer has updated the data link registers T1RSLC1-3 with the latest message data from the incoming data stream. Once the RSLC96 bit is set, the user will have 9ms (or until the next RSLC96 interrupt) to retrieve the most recent message data from the T1RSLC1-3 registers. Note that RSLC96 will not set if the DS26518 is unable to detect the 12-bit SLC-96 alignment pattern. 58 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.5 T1 Data Link 9.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller The DS26518 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. Table 9-19 shows the registers related to the transmit bit-oriented code. Table 9-19. Registers Related to T1 Transmit BOC REGISTER Transmit BOC Register (T1TBOC) Transmit HDLC Control Register 2 (THC2) Transmit Control Register 1(TCR1) FRAMER 1 ADDRESSES 163h 113h 181h FUNCTION Transmit bit-oriented message code register. Bit to enable sending of transmit BOC. Determines the sourcing of the F-bit. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. Bits 0 to 5 in the T1TBOC register contain the BOC message to be transmitted. Setting SBOC = 1 (THC2.6) causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as SBOC is set. Note that the TFPT (TCR1.6) control bit must be set to zero for the BOC message to overwrite F-bit information being sampled on TSERn. 9.9.5.1.1 To Transmit a BOC 1) Write 6-bit code into the T1TBOC register. 2) Set SBOC bit in THC2 = 1. 9.9.5.2 Receive Bit-Oriented Code (BOC) Controller The DS26528 framers contain a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1, ESF mode in the data link bits. Table 9-20 shows the registers related to the receive BOC operation. Table 9-20. Registers Related to T1 Receive BOC REGISTER Receive BOC Control Register (T1RBOCC) Receive BOC Register (T1RBOC) Receive Latched Status Register 7(RLS7) Receive Interrupt Mask Register 7 (RIM7) FRAMER 1 ADDRESSES 015h 063h 096h 0A6h FUNCTION Controls the receive BOC function. Receive bit-oriented message. Indicates changes to the receive bit-oriented messages. Mask bits for RBOC for generation of interrupts. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. In ESF mode, the DS26518 continuously monitors the receive message bits for a valid BOC message. The BOC detect (BD) status bit at RLS7.0 will be set once a valid message has been detected for time determined by the receive BOC filter bits RBF0 and RBF1 in the T1RBOCC register. The 6-bit BOC message will be available in the RBOC register. Once the user has cleared the BD bit, it will remain clear until a new BOC is detected (or the same BOC is detected following a BOC clear event). The BOC clear (BC) bit at RLS7.1 is set when a valid BOC is no longer being detected for a time determined by the receive BOC disintegration bits RBD0 and RBD1 in the T1RBOCC register. The BD and BC status bits can create a hardware interrupt on the INTB signal as enabled by the associated interrupt mask bits in the RIM7 register. 59 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.5.3 Legacy T1 Transmit FDL It is recommended that the DS26518's built-in BOC or HDLC controllers be used for most applications requiring access to the FDL. Table 9-21 shows the registers related to control of the transmit FDL. Table 9-21. Registers Related to T1 Transmit FDL REGISTER Transmit FDL Register (T1TFDL) Transmit Control Register 2 (T1.TCR2) Transmit Latched Status Register 2 (TLS2) Transmit Interrupt Mask Register 2 (TIM2) FRAMER 1 ADDRESSES 162h 182h 191h 1A1h FUNCTION FDL code used to insert transmit FDL. Defines the source of the FDL. Transmit FDL empty bit. Mask bit for TFDL empty. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. When enabled with T1.TCR2.7, the transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL Register (T1TFDL). When a new value is written to the T1TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full eight bits has been shifted out, the framer will signal the host controller that the buffer is empty and that more data is needed by setting the TLS2.4 bit to a one. INTB will also toggle low if enabled via TIM2.4. The user has 2ms to update the T1TFDL with a new value. If the T1TFDL is not updated, the old value in the T1TFDL register will be transmitted once again. Note that in this mode, no zero stuffing will be applied to the FDL data. It is strongly suggested that the HDLC controller be used for FDL messaging applications. In the D4 framing mode, the framer uses the T1TFDL register to insert the Fs framing pattern. To accomplish this the T1TFDL register must be programmed to 1Ch and T1.TCR2.7 should be set to 0 (source Fs data from the T1TFDL register). The T1TFDL register contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used. 9.9.5.4 Legacy T1 Receive FDL It is recommended that the DS26518's built-in BOC or HDLC controllers be used for most applications requiring access to the FDL. Table 9-22 shows the registers related to the receive FDL. Table 9-22. Registers Related to T1 Receive FDL REGISTER Receive FDL Register (T1RFDL) Receive Latched Status Register 7(RLS7) Receive Interrupt Mask Register 7(RIM7) FRAMER 1 ADDRESSES 062h 096h 0A6h FUNCTION FDL code used to receive FDL. Receive FDL full bit is in this register. Mask bit for RFDL full. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL Register (T1RFDL). Since the T1RFDL is 8 bits in length, it will fill up every 2ms (8 times 250s). The framer will signal an external controller that the buffer has filled via the RLS7.2 bit. If enabled via RIM7.2, the INTB pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. Note that no zero destuffing is applied to the for the data provided through the T1RFDL register. The T1RFDL register reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, T1RFDL updates on multiframe boundaries and reports only the Fs bits. 60 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.6 E1 Data Link Table 9-23 shows the registers related to E1 data link. Table 9-23. Registers Related to E1 Data Link REGISTER E1 Receive Align Frame Register (E1RAF) E1 Receive Non-Align Frame Register Register (E1RNAF) E1 Received Si Bits of the Align Frame Register (E1RsiAF) Received Si Bits of the Non-Align Frame Register E1RSiNAF) Received Sa4 to Sa8 Bits Register (E1RSa4 to E1RSa8) Transmit Align Frame Register (E1TAF) Transmit Non-Align Frame Register (E1TNAF) Transmit Si Bits of the Align Frame Register (E1TSiAF) Transmit Si Bits of the Non-Align Frame Register (E1TSiNAF) Transmit Sa4 to Sa8 Bits Register (E1TSa4 to E1TSa8) E1 Transmit Sa-Bit Control Register (E1TSACR) FRAMER 1 ADDRESSES 064h 065h 066h 067h 069h, 06Ah, 06Bh, 06Ch, 06Dh 164h 165h 166h 167h 169h, 16Ah, 16Bh, 16Ch, 16Dh 114h FUNCTION Receive frame alignment register. Receive non-frame alignment register. Receive Si bits of the frame alignment frames. Receive Si bits of the non-frame alignment frames. Receive Sa bits. Transmit align frame register. Transmit non-align frame register. Transmit Si bits of the frame alignment frames. Transmit Si bits of the non-frame alignment frames. Transmit Sa4 to Sa8. Transmit sources of Sa control. Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8. 61 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.6.1 Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode) The DS26518, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods. The first involves using the internal E1RAF/E1RNAF and E1TAF/E1TNAF registers. The second method involves an expanded version of the first method. 9.9.6.1.1 Internal Register Scheme Based on Double-Frame (Method 1) On the receive side, the E1RAF and E1RNAF registers will always report the data as it received in the Sa and Si bit locations. The E1RAFand E1RNAF registers are updated on align frame boundaries. The setting of the Receive Align Frame bit in Receive Latched Status Register 2 (RLS2.0) will indicate that the contents of the RAF and RNAF have been updated. The host can use the RLS2.0 bit to know when to read the E1RAF and E1RNAF registers. The host has 250s to retrieve the data before it is lost. 9.9.6.1.2 Internal Register Scheme Based on CRC-4 Multiframe (Receive) On the receive side, there is a set of eight registers (E1RsiAF, E1RSiNAF, E1RRA, E1RSa4 to E1RSa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC-4 multiframe bit in Receive Latched Status Register 2 (RLS2.1). The host can use the RLS2.1 bit to know when to read these registers. The user has 2ms to retrieve the data before it is lost. See the register descriptions for additional information. 9.9.6.1.3 Internal Register Scheme Based on CRC-4 Multiframe (Transmit) On the transmit side there is a set of eight registers (E1TSiAF, E1TSiNAF, E1TRA, E1TSa4 to E1TSa8) that, via the E1 Transmit Sa-Bit Control Register (E1TSACR), can be programmed to insert both Si and Sa data. Data is sampled from these registers with the setting of the transmit multiframe bit in Transmit Latched Status Register 1 (TLS1.3). The host can use the TLS1.3 bit to know when to update these registers. It has 2ms to update the data or else the old data will be retransmitted. See the register descriptions in Section 10 for more information. 9.9.6.2 Sa-Bit Monitoring and Reporting In addition to the registers outlined above, the DS26518 provides status and interrupt capability in order to detect changes in the state of selected Sa bits. The E1RSAIMR register can be used to select which Sa bits are monitored for a change of state. When a change of state is detected in one of the enabled Sa bit positions, a status bit is set in the RLS7 register via the SaXCD bit (bit 0). This status bit can in turn be used to generate an interrupt by unmasking RIM7.0 (SaXCD). If multiple Sa bits have been enabled, the user can read the SaBITS register at address 06Eh to determine the current value of each Sa bit. For the Sa6 bits, additional support is available to detect specific codewords per ETS 300 233. The Sa6CODE register will report the received Sa6 codeword. The codeword must be stable for a period of three submultiframes and be different from the previous stored value in order to be updated in this register. See the Sa6CODE register description for further details on the operation of this register and the values reported in it. An additional status bit is provided in RLS7.1 (Sa6CD) to indicate if the received Sa6 codeword has changed. A mask bit is provided for this status bit in RIM7 to allow for interrupt generation when enabled. 9.9.7 Maintenance and Alarms The DS26518 provides extensive functions for alarm detection and generation. It also provides diagnostic functions for monitoring of performance and sending of diagnostic information: * Real-time and latched status bits, interrupts and interrupt mask for transmitter and receiver * LOS detection * RIA detection and generation * Error counters * DS0 monitoring * Milliwatt generation and detection * Slip buffer status for transmit and receive 62 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 9-24 shows some of the registers related to maintenance and alarms. Table 9-24. Registers Related to Maintenance and Alarms REGISTER Receive Real-Time Status Register 1 (RRTS1) Receive Interrupt Mask Register 1(RIM1) Receive Latched Status Register 2 (RLS2) Receive Real-Time Status Register 3 (RRTS3) Receive Latched Status Register 3 (RLS3) Receive Interrupt Mask Register 3 (RIM3) Receive Interrupt Mask Register 4 (RIM4) Receive Latched Status Register 7 (RLS7) Receive Interrupt Mask Register 7 (RIM7) Transmit Latched Status Register 1 (TLS1) Transmit Latched Status Register 3 (Synchronizer) (TLS3) Receive DS0 Monitor Register (RDS0M) Error-Counter Configuration Register (ERCNT) Line Code Violation Count Register 1 (LCVCR1) Line Code Violation Count Register 2 (LCVCR2) Path Code Violation Count Register 1 (PCVCR1) Path Code Violation Count Register 2 (PCVCR2) Frames Out of Sync Count Register 1 (FOSCR1) Frames Out of Sync Count Register 2 (FOSCR2) E-Bit Count Register 1 (E1EBCR1) E-Bit Count Register 2 (E1EBCR2) FRAMER 1 ADDRESSES 0B0h 0A0h 091h 0B2h 092h 0A2h 0A3h 096h 0A6h 190h 192h 060h 086h 050h 051h 052h 053h 054h 055h 056h 057h FUNCTION Real-time receive status 1. Real-time interrupt mask 1. Real-time latched status 2. Real-time receive status 2. Real-time latched status 3. Real-time interrupt mask 3. Real-time interrupt mask 3. Real-time latched status 7. Real-time interrupt mask 7. Loss of transmit clock status, etc. Loss of frame status. Receive DS0 monitor. Configuration of the error counters. Line code violation counter 1. Line code violation counter 2. Receive path code violation counter 1. Receive path code violation counter 2. Receive frame out of sync counter 1 Receive frame out of sync counter 2 E-bit count register 1. E-bit count register 2. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. 63 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.7.1 Status and Information Bit Operation When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate a hardware interrupt via the INTB signal. 9.9.7.1.1 Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real-time bits will remain stable, and valid during the host read operation. The current value of the internal status signals can be read at any time from the real-time status registers without changing any the latched status register bits. 9.9.7.1.2 Latched Bits When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user. These bits typically respond on a change-of-state for an alarm, condition, or event; and operate in a read-then-write fashion. The user should read the value of the desired status bit, and then write a 1 to that particular bit location in order to clear the latched value (write a 0 to locations not to be cleared). Once the bit is cleared, it will not be set again until the event has occurred again. 9.9.7.1.3 Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Receive Interrupt Mask Registers (RIM1, RIM3, RIM4, RIM5, RIM7). When unmasked, the INTB signal will be forced low when the enabled event or condition occurs. The INTB pin will be allowed to return high (if no other unmasked interrupts are present) when the user reads then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INTB pin will clear even if the alarm is still present. Note that some conditions may have multiple status indications. For example, receive loss of frame (RLOF) provides the following indications: Real-time indication that the receiver is not synchronized with incoming data stream. Read-only bit that remains high as long as the condition is present. Latched indication that the receiver has loss synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (rising edge detect of RRTS1.0). Latched indication that the receiver has reacquired synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (falling edge detect of RRTS1.0). RRTS1.0 (RLOF) RLS1.0 (RLOFD) RLS1.4 (RLOFC) 64 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.8 Alarms Table 9-25. T1 Alarm Criteria ALARM AIS (Blue Alarm) (See Note 1) 1) D4 Bit 2 Mode (T1RCR2.0 = 0) 2) D4 12th F-Bit Mode (T1RCR2.0 = 1) (Note: This mode is also referred to as the "Japanese Yellow Alarm.") 3) ESF Mode SET CRITERIA When over a 3ms window, 4 or fewer zeros are received. When bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences. When the 12th framing bit is set to one for two consecutive occurrences. CLEAR CRITERIA When over a 3ms window, 5 or more zeros are received. When bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences. When the 12th framing bit is set to zero for two consecutive occurrences. RAI (Yellow Alarm) When 16 consecutive patterns of 00FF appear in the FDL. When 16 consecutive patterns of FFFF appear in the FDL. When 192 consecutive zeros are received. 4) J1 ESF Mode (J1 LFA) LOS (Loss of Signal) (Note: This alarm is also referred to as receive carrier loss (RCL).) Note 1: When 14 or fewer patterns of 00FF hex out of 16 possible appear in the FDL. When 14 or fewer patterns of FFFF hex out of 16 possible appear in the FDL. When 14 or more ones out of 112 possible bit positions are received starting with the first one received. The definition of the Alarm Indication Signal (Blue Alarm) is an unframed all-ones signal. AIS detectors should be able to operate properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all-ones signal. The AIS alarm criteria in the DS26518 has been set to achieve this performance. It is recommended that the RAIS bit be qualified with the RLOF bit. The following terms are equivalent: RAIS = Blue Alarm RLOS = RCL RLOF = Loss of Frame (conventionally RLOS for Dallas Semiconductor devices) RRAI = Yellow Alarm Note 2: 9.9.8.1 Transmit RAI Table 9-26 shows the registers related to the transmit RAI (Yellow Alarm). Table 9-26. Registers Related to Transmit RAI (Yellow Alarm) REGISTER Transmit Control Register 1 (TCR1.TRAI) Transmit Control Register 2 (T1.TCR2.TRAIS) Transmit Control Register 4 (TCR4.TRAIM) Transmit Control Register 2 (E1.TCR2.ARA) FRAMER 1 ADDRESSES 181h 182h FUNCTION Enable transmission of RAI. Select RAI to be T1 or J1. 186h Select RAI to be normal or RAI-CI for T1 ESF mode. Selects automatic remote alarm generation in E1 mode. 182h Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. 65 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.8.2 Receive RAI Table 9-27 shows the registers related to the receive RAI (Yellow Alarm). Table 9-27. Registers Related to Receive RAI (Yellow Alarm) REGISTER Receive Control Register 2 (T1RCR2.RRAIS) Receive Control Register 2 (T1RCR2.RAIIE) FRAMER 1 ADDRESSES 014h 014h FUNCTION Select RAI to be T1 or J1. Integration Enable for T1 ESF Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. 9.9.8.3 E1 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (E1.TCR2.AAIS = 1), the device monitors the receive-side framer to determine if any of the following conditions are present/loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer will either force an AIS. When automatic RAI generation is enabled (E1.TCR2.ARA = 1), the framer monitors the receive side to determine if any of the following conditions are present/ loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal) or if CRC-4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC-4 is enabled). If any one (or more) of the above conditions is present, then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 and ITU-T G.706 specifications. Note: It is an illegal state to have both automatic AIS generation and automatic remote alarm generation enabled at the same time. 9.9.8.4 Receive AIS-CI and RAI-CI Detection AIS-CI is a repetitive pattern of 1.26 seconds. It consists of 1.11 seconds of an unframed all-ones pattern and 0.15 seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in length in which, if the first bit is numbered bit 0, bits 3088, 3474 and 5790 are logical zeros and all other bits in the pattern are logical ones (T1.403). AIS-CI is an unframed pattern, so it is defined for all T1 framing formats. The RAIS-CI bit is set when the AIS-CI pattern has been detected and RAIS (RRTS1.2) is set. RAIS-CI is a latched bit that should be cleared by the host when read. RAIS-CI will continue to set approximately every 1.2 seconds that the condition is present. The host will need to `poll' the bit, in conjunction with the normal AIS indicators to determine when the condition has cleared. RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of "00000000 11111111" (right-to-left ) with 90 ms of "00111110 11111111". The RRAICI bit is set when a bit oriented code of "00111110 11111111" is detected while RRAI (RRTS1.3) is set. The RRAICI detector uses the receive BOC filter bits (RBF0 and RBF1) located in RBOCC to determine the integration time for RAI-CI detection. Like RAIS-CI, the RRAI-CI bit is latched and should be cleared by the host when read. RRAICI will continue to set approximately every 1.1 seconds that the condition is present. The host will need to "poll" the bit, in conjunction with the normal RAI indicators to determine when the condition has cleared. It may be useful to enable the 200ms ESF RAI integration time with the RAIIE control bit (T1RCR2.1) in networks that utilize RAI-CI. 9.9.8.5 T1 Receive-Side Digital Milliwatt Code Generation Receive-side digital milliwatt code generation involves using the T1 Receive Digital Milliwatt Registers (T1RDMWE1-3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital milliwatt pattern. The digital milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMWEx registers represents a particular channel. If a bit is set to a one, then the receive data in that channel will be replaced with the digital milliwatt code. If a bit is set to zero, no replacement occurs. 66 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.9 Error Count Registers The DS26518 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only) or manually. See the Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers. All four counters will saturate at their respective maximum counts and they will not roll over. (Note: Only the Line Code Violation Count Register has the potential to overflow but the bit error would have to exceed 10E-2 before this would occur.) The DS26518 can share the one-second timer from Port 1 across all ports. All DS26518 error/performance counters can be configured to update on the shared one-second source or a separate manual update signal input. See the ERCNT register for more information. By allowing multiple framer cores to synchronously latch their counters, the host software can be streamlined to read and process performance information from multiple spans in a more controlled manner. 9.9.9.1 Line Code Violation Count Register (LCVCR) Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of the same polarity. In T1 mode, if the B8ZS mode is set for the receive side, then B8ZS codewords are not counted as BPVs. In E1 mode, if the HDB3 mode is set for the receive side, then HDB3 codewords are not counted as BPVs. If ERCNT.0 is set, then the LVC counts code violations as defined in ITU-T O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving B8ZS or HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10E-2 before the VCR would saturate. See Table 9-28 and Table 9-29 for details of exactly what the LCVCRs count. Table 9-28. T1 Line Code Violation Counting Options COUNT EXCESSIVE ZEROS? (ERCNT.0) No Yes No Yes B8ZS ENABLED? (RCR1.6) No No Yes Yes WHAT IS COUNTED IN LCVCR1, LCVCR2 BPVs BPVs + 16 consecutive zeros BPVs (B8ZS/HDB3 codewords not counted) BPVs + 8 consecutive zeros Table 9-29. E1 Line Code Violation Counting Options E1 CODE VIOLATION SELECT (ERCNT.0) 0 1 WHAT IS COUNTED IN LCVCR1, LCVCR2 BPVs CVs 67 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.9.2 Path Code Violation Count Register (PCVCR) In T1 operation, the Path Code Violation Count Register records either Ft, Fs, or CRC-6 errors. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR will record errors in the CRC-6 codewords. When set to operate in the T1 D4 framing mode, PCVCR will count errors in the Ft framing bit position. Via the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOF = 1) conditions. See Table 9-30 for a detailed description of exactly what errors the PCVCR counts in T1 operation. In E1 operation, the Path Code Violation Count Register records CRC-4 errors. Since the maximum CRC-4 count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC-4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. The Path Code Violation Count Register 1 (PCVCR1) is the most significant word and the Path Code Violation Count Register 2 (PCVCR2) is the least significant word of a 16-bit counter that records path violations (PVs). Table 9-30. T1 Path Code Violation Counting Arrangements FRAMING MODE D4 D4 ESF COUNT Fs ERRORS? No Yes Don't Care WHAT IS COUNTED IN PCVCR1, PCVCR2? Errors in the Ft pattern Errors in both the Ft and Fs patterns Errors in the CRC-6 codewords 9.9.9.3 Frames Out of Sync Count Register (FOSCR) The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss of frame count (LOFC) and ESF error events as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOF = 1) conditions. The FOSCR has alternate operating mode whereby it will count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the FOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOF = 1) conditions. See Table 9-31 for a detailed description of what the FOSCR is capable of counting. In E1 mode, the FOSCR counts word errors in the frame alignment signal in time slot 0. This counter is disabled when RLOF is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC-4 multiframe level. Since the maximum FAS word error count in a onesecond period is 4000, this counter cannot saturate. The Frames Out of Sync Count Register 1 (FOSCR1) is the most significant word and the Frames Out of Sync Count Register 2 FOSCR2 is the least significant word of a 16-bit counter that records frames out of sync. Table 9-31. T1 Frames Out of Sync Counting Arrangements FRAMING MODE (RCR1.5) D4 D4 ESF ESF COUNT MOS OR F-BIT ERRORS (ERCNT.1) MOS F-Bit MOS F-Bit WHAT IS COUNTED IN FOSCR1, FOSCR2 Number of multiframes out of sync Errors in the Ft pattern Number of multiframes out of sync Errors in the FPS pattern 9.9.9.4 E-Bit Counter (EBCR) This counter is only available in E1 mode. The E-Bit Count Register 1 (E1EBCR1) is the most significant word and the E-Bit Count Register 2 (E1EBCR2) is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC-4 multiframe. These count registers will increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC-4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. 68 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.10 DS0 Monitoring Function The DS26518 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. Table 9-32 shows the registers related to the control of transmit and receive DS0. Table 9-32. Registers Related to DS0 Monitoring REGISTER Transmit DS0 Channel Monitor Select Register (TDS0SEL) Transmit DS0 Monitor Register (TDS0M) Receive Channel Monitor Select Register (RDS0SEL) Receive DS0 Monitor Register (RDS0M) FRAMER 1 ADDRESSES 189h 1BBh 012h 060h FUNCTION Transmit channel to be monitored. Monitored data. Receive channel to be monitored. Monitored data. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM[4:0] bits in the TDS0SEL register. In the receive direction, the RCM[4:0] bits in the RDS0SEL register need to be properly set. The DS0 channel pointed to by the TCM[4:0] bits will appear in the Transmit DS0 Monitor Register (TDS0M) and the DS0 channel pointed to by the RCM[4:0] bits will appear in the Receive DS0 Monitor Register (RDS0M). The TCM[4:0] and RCM[4:0] bits should be programmed with the decimal decode of the appropriate T1or E1 channel. T1 channels 1 to 24 map to register values 0 to 23. E1 channels 1 to 32 map to register values 0 to 31. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into TDS0SEL and RDS0SEL: TCM4 = 0 RCM4 = 0 TCM3 = 0 RCM3 = 1 TCM2 = 1 RCM2 = 1 TCM1 = 0 RCM1 = 1 TCM0 = 1 RCM0 = 0 69 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.11 Transmit Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Transmit Idle Code Definition Registers (TIDR1-32) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1-4) are used to enable idle code replacement on a perchannel basis. 9.9.12 Receive Per-Channel Idle Code Insertion Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Receive Idle Code Definition Registers (RIDR1-32) are provided to set the 8-bit idle code for each channel. The Receive Channel Idle Code Enable Registers (RCICE1-4) are used to enable idle code replacement on a perchannel basis. 9.9.13 Per-Channel Loopback The Per-Channel Loopback Enable Registers (PCL1-4) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLKn to TCLKn and RFSYNCn to TSYNCn. There are no restrictions on which channels can be looped back or on how many channels can be looped back. Each of the bit positions in PCL1-4) represents a DS0 channel in the outgoing frame. When these bits are set to a one, data from the corresponding receive channel will replace the data on TSERn for that channel. 9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) The DS26518 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSERn will already have the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa-bit positions and this change in data content will be used to modify the CRC-4 checksum. This modification, however, will not corrupt any error information the original CRC-4 checksum may contain. In this mode of operation, TSYNCn must be configured to multiframe mode. The data at TSERn must be aligned to the TSYNCn signal. If TSYNCn is an input then the user must assert TSYNCn aligned at the beginning of the multiframe relative to TSERn. If TSYNCn is an output, the user must multiframe align the data presented to TSERn. This mode is enabled with the TCR3.0 control bit (CRC4R). Note that the E1 transmitter must already be enabled for CRC insertion with the TCR1.0 control bit (TCRC4). See Figure 9-16. Figure 9-16. CRC-4 Recalculate Method TTIPn/TRINGn INSERT NEW CRC-4 CODE EXTRACT OLD CRC-4 CODE TSERn + CRC-4 CALCULATOR XOR MODIFY Sa-BIT POSITIONS NEW Sa-BIT DATA 70 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.15 T1 Programmable In-Band Loop Code Generator The DS26518 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 9-33. Registers Related to T1 In-Band Loop Code Generator REGISTER Transmit Code Definition Register 1 (T1TCD1) Transmit Code Definition Register 2 (T1TCD2) Transmit Control Register 3 (TCR3) Transmit Control Register 4 (TCR4) FRAMER 1 ADDRESSES 1ACh 1ADh 183h 186h FUNCTION Pattern to be sent for loop code. Length of the pattern to be sent. TLOOP bit for control of number of patterns being sent. Length of the code being sent. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition Registers (T1TCD1 and T1TCD2) and select the proper length of the pattern by setting the TC0 and TC1 bits in Transmit Control Register 4 (TCR4). When generating a 1-, 2-, 4-, 8-, or 16-bit pattern both T1TCD1 and T1TCD2 must be filled with the proper code. Generation of a 3-, 5-, 6-, and 7-bit pattern only requires T1TCD1 to be filled. Once this is accomplished, the pattern will be transmitted as long as the TLOOP control bit (TCR3.0) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the framer will overwrite the repeating pattern once every 193 bits to allow the F-bit position to be sent. As an example, to transmit the standard "loop-up" code for Channel Service Units (CSUs), which is a repeating pattern of ...10000100001..., set TCD1 = 80h, TC0 = 0, TC1 = 0, and TCR3.0 = 1. 71 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.16 T1 Programmable In-Band Loop Code Detection The DS26518 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 9-34. Registers Related to T1 In-Band Loop Code Detection REGISTER Receive In-Band Code Control Register (T1RIBCC) Receive Up Code Definition Register 1 (T1RUPCD1) Receive Up Code Definition Register 2 (T1RUPCD2) Receive Down Code Definition Register 1 (T1RDNCD1) Receive Down Code Definition Register 2 (T1RDNCD2) Receive Spare Code Register 1 (T1RSCD1) Receive Spare Code Register 2 (T1RSCD2) Receive Real-Time Status Register 3 (RRTS3) Receive Latched Status Register 3 (RLS3) Receive Interrupt Mask Register 3 (RIM3) FRAMER 1 ADDRESSES 082h 0ACh 0ADh 0AEh 0AFh 09Ch 09Dh 0B2h 092h 0A2h FUNCTION Used for selecting length of receive inband loop code register. Receive up code definition register 1. Receive up code definition register 2. Receive down code definition register 1. Receive up code definition register 2. Receive spare code register 1. Receive spare code register 2. Real-time loop code detect. Latched loop code detect bits. Mask for latched loop code detect bits. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. The framer has three programmable pattern detectors. Typically, two of the detectors are used for "loop-up" and "loop-down" code detection. The user will program the codes to be detected in the Receive Up Code Definition Registers 1 and 2 (T1RUPCD1 and T1RUPCD2) and the Receive Down Code Definition Registers 1 and 2 (T1RDNCD1 and T1RDNCD2) registers and the length of each pattern will be selected via the T1RIBCC register. There is a third detector (spare) and it is defined and controlled via the T1RSCD1/T1RSCD2 and T1RSCC registers. When detecting a 16-bit pattern both receive code definition registers are used together to form a 16-bit register. For 8-bit patterns, both receive code definition registers will be filled with the same value. Detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code definition register to be filled. The framer will detect repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10E-2. The detectors can handle both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of receive code definition register resets the integration period for that detector. The code detector has a nominal integration period of 48ms. Hence, after about 48ms of receiving a valid code, the proper status bit (LUP, LDN, and LSP) will be set to a one. Note that real-time status bits, as well as latched set and clear bits are available for LUP, LDN and LSP (RRTS3 and RLS3). Normally codes are sent for a period of 5 seconds. It is recommend that the software poll the framer every 50ms to 100ms until 5 seconds has elapsed to ensure that the code is continuously present. 72 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.9.17 Framer Payload Loopbacks The framer, payload, and remote loopbacks are controlled by RCR3. Table 9-35. Register Related to Framer Payload Loopbacks RECEIVE CONTROL REGISTER 3 (RCR3) Framer Loopback Payload Loopback Remote Loopback FRAMER 1 ADDRESSES 083h 083h 083h FUNCTION Transmit data output from the framer is looped back to the receiver. The 192-bit payload data is looped back to the transmitter. Data recovered by the receiver is looped back to the transmitter. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. 73 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.10 HDLC Controllers 9.10.1 Receive HDLC Controller This device has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). The HDLC controller has 64-byte FIFO buffer in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 mode). The HDLC controller performs all the necessary overhead for generating and receiving performance report messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention. Table 9-36 shows the registers related to the HDLC. Table 9-36. Registers Related to the HDLC REGISTER Receive HDLC Control Register (RHC) Receive HDLC Bit Suppress Register (RHBSE) Receive HDLC FIFO Control Register (RHFC) Receive HDLC Packet Bytes Available Register (RHPBA) Receive HDLC FIFO Register (RHF) Receive Real-Time Status Register 5 (RRTS5) Receive Latched Status Register 5 (RLS5) Receive Interrupt Mask Register 5 (RIM5) Transmit HDLC Control Register 1(THC1) Transmit HDLC Bit Suppress Register (THBSE) Transmit HDLC Control Register 2 (THC2) Transmit HDLC FIFO Control Register (THFC) Transmit Real-Time Status Register 2 (TRTS2) Transmit HDLC Latched Status Register 2 (TLS2) Transmit Interrupt Mask Register 2 (HDLC) Register (TIM2) Transmit HDLC FIFO Buffer Available Register (TFBA) Transmit HDLC FIFO Register (THF) FRAMER 1 ADDRESSES 010h 011h 087h 0B5h 0B6h 0B4h 094h 0A4h 110h 111h 113h 187h 1B1h 191h 1A1h 1B3h 1B4h FUNCTION Mapping of the HDLC to DS0 or FDL. Receive HDLC bit suppression register. Determines the length of the receive HDLC FIFO. Tells the user how many bytes are available in the teceive HDLC FIFO. The actual FIFO data. Indicates the FIFO status. Latched status. Interrupt mask for interrupt generation for the latched status. Miscellaneous transmit HDLC control. Transmit HDLC bit suppress for bits not to be used. HDLC to DS0 channel selection and other control. Used to control the transmit HDLC FIFO. Indicates the real-time status of the transmit HDLC FIFO. Indicates the FIFO status. Interrupt mask for the latched status. Indicates the number of bytes that can be written into the transmit FIFO. Transmit HDLC FIFO. Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8. 74 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.10.1.1 HDLC FIFO Control Control of the transmit and receive FIFOs is accomplished via the Receive HDLC FIFO Control (RHFC) and Transmit HDLC FIFO Control (THFC) registers. The FIFO control registers set the watermarks for the FIFO. When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) will be set. RHWM and THRM are real-time bits and will remain set as long as the FIFO's write pointer is above the watermark. When the transmit FIFO empties below the low watermark, the TLWM bit in the TRTS2 register will be set. TLWM is a real-time bit and will remain set as long as the transmit FIFO's write pointer is below the watermark. If enabled, this condition can also cause an interrupt via the INTB pin. If the receive HDLC FIFO does overrun the current packet being processed is dropped. The receive FIFO is emptied. The packet status bit in RRTS5 and RLS5.5 (ROVR) indicate an overrun. 9.10.1.2 Receive Packet Bytes Available The lower 7 bits of the Receive HDLC Packet Bytes Available Register (RHPBA) indicates the number of bytes (0 to 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message. This value will refer to one of four possibilities, the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this register the host then checks the HDLC status registers for detailed message status. If the value in the RHPBA register refers to the beginning portion of a message or continuation of a message, then the MSB of the RHPBA register will return a value of 1. This indicates that the host can safely read the number of bytes returned by the lower 7 bits of the RHPBA register, but there is no need to check the information register since the packet has not yet terminated (successfully or otherwise). 9.10.1.3 HDLC Status and Information RRTS5, RLS5, and TLS2 provide status information for the HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these registers are latched and some are real-time bits that are not latched. This section contains register descriptions that list which bits are latched and which are real-time. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads and clears that bit. The bit will be cleared when a 1 is written to the bit and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear. The HDLC status registers RLS5 and TLS2 have the ability to initiate a hardware interrupt via the INTB output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the HDLC interrupt mask registers RIM5 and TIM2. Interrupts will force the INTB signal low when the event occurs. The INTB pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. 9.10.1.4 HDLC Receive Example The HDLC status registers in the DS26518 allow for flexible software interface to meet the user's preferences. When receiving HDLC messages, the host can choose to be interrupt driven, to poll to desired status registers, or a combination of polling and interrupt processes can be used. An example routine for using the DS26518 HDLC receiver is given in Figure 9-17. 75 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-17. HDLC Message Receive Example Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.6) Start New Message Buffer Enable Interrupts RPE and RHWM Interrupt? NO No Action Required Work Another Process. YES Read Register RHPBA Start New Message Buffer NO MS = 1? (MS = RHPBA[7]) YES Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0] Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0] Read RRTS5 for Packet Status (PS2..0) Take appropriate action 76 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.10.2 Transmit HDLC Controller 9.10.2.1 FIFO Information The Transmit HDLC FIFO Buffer Available Register (TFBA) indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable during the read cycle. 9.10.2.2 HDLC Transmit Example The HDLC status registers in the DS26518 allow for flexible software interface to meet the user's preferences. When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes can be used. Figure 9-18 shows an example routine for using the DS26518 HDLC receiver. 77 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-18. HDLC Message Transmit Example Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC.5) Enable TLWM Interrupt and Verify TLWM Clear Set TEOM (THC1.2) Read TFBA N = TFBA[6..0] Push Last Byte into Tx FIFO Push Message Byte into Tx HDLC FIFO (THF) Loop N Last Byte of Message? NO NO YES Enable TMEND Interrupt TMEND Interrupt? YES Read TUDR Status Bit NO A TLWM Interrupt? YES A NO TUDR = 1 A YES No Action Required Work Another Process Disable TMEND Interrupt Prepare New Message Disable TMEND Interrupt Resend Message 78 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.11 Power-Supply Decoupling DECOUPLING CAPACITANCE 0.01F + 0.1F + 1F + 10F 0.01F + 0.1F + 1F + 10F -- -- It is recommended to use one 0.1F cap for each ATVDD/ATVSS pair (8 total), one 1F for every two ATVDD/ATVSS pairs (4 total), and two 10F capacitors for the analog transmit supply pins. These capacitors should be located as close to the intended power pins as possible. It is recommended to use one 0.1F cap for each ARVDD/ARVSS pair (8 total), one 1F for every two ARVDD/ARVSS pairs (4 total), and two 10F capacitors for the analog receive supply pins. These capacitors should be located as close to the intended power pins as possible. -- NOTES Table 9-37. Recommended Supply Decoupling SUPPLY PINS DVDD33/DVSS DVDD18/DVSS ATVDD/ATVSS 0.1F (x8) + 1F (x4) + 10F (x2) ARVDD/ARVSS 0.1F (x8) + 1F (x4) + 10F (x2) ACVDD/ACVSS 0.1F + 1F + 10F 79 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12 Line Interface Units (LIUs) The DS26518 has eight identical LIU transmit and receive front-ends for each of the eight framers. Each LIU contains three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock and data recovery; and the jitter attenuator. The DS26518 LIUs can switch between T1 or E1 networks without changing any external components on either the transmit or receive side. Figure 9-19 shows a recommended circuit for software selected termination with protection. In this configuration the device can connect to 100 T1 twisted pair, 110 J1 twisted pair, 75 or 120 E1 twisted pair without additional component changes. The signals between the framer and LIU are not accessible by the user, thus the framer and LIU cannot be separated. The transmitters have fast high-impedance capability and can be individually powered down. The DS26518's transmit waveforms meet the corresponding G.703 and T1.102 specifications. Internal softwareselectable transmit termination is provided for 100 T1 twisted pair, 110 J1 twisted pair, 120 E1 twisted pair and 75 E1 coaxial applications. The receiver can connect to 100 T1 twisted pair, 110 J1 twisted pair, 120 E1 twisted pair, and 75 E1 coaxial. The receive LIU can function with a receive signal attenuation of up to 36dB for T1 mode and 43dB for E1 mode. The receiver sensitivity is programmable from 12dB to 43dB of cable loss. Also a monitor gain setting can be enabled to provide 14dB, 20dB, 26dB, and 32dB of resistive gain. 80 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-19. Network Connection--Longitudinal Protection TX TIP F1 T3 S3 S7 S4 T1 S1 1 uF TTIPn 560 pF TX RING TRINGn F2 2:1 DS26518 RX TIP F3 T4 S5 S8 S6 T2 RTIPn S2 RT RRINGn RX RING F4 1:1 NAME F1 to F4 S1, S2 S3, S4, S5, S6 S7, S8 T1 and T2 T3 and T4 RT Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: DESCRIPTION 1.25A Slow Blow Fuse 1.25A Slow Blow Fuse 25V (max) Transient Suppressor 180V (max) Transient Suppressor 40V (max) Transient Suppressor Transformer 1:1CT and 1:2CT (3.3V, SMT) Dual Common-Mode Choke (SMT) Termination Resistor (120, 110, 100, or 75) PART SMP 1.25 F1250T P0080SA MC P1800SC MC P0300SC MC PE-68678 PE-65857 -- MANUFACTURER Bel Fuse Teccor Electronics Teccor Electronics Teccor Electronics Teccor Electronics Pulse Engineering Pulse Engineering -- NOTES 5 5 1, 5 1, 4, 5 1, 5 2, 3, 5 5 -- Changing S7 and S8 to P1800SC devices provides symmetrical voltage suppresion between tip, ring, and ground. The layout from the transformers to the network interface is critical. Traces should be at least 25 mils wide and separated from other circuit lines by at least 150 mils. The area under this portion of the circuit should not contain power planes. Some T1 (never in E1) applications source or sink power from the network-side center taps of the Rx/Tx transformers. The ground trace connected to the S3/S4 pair and the S5/S6 pair should be at least 50 mils wide to conduct the extra current from a longitudinal power-cross event. Alternative component recommendations and line interface circuits can be found by contacting telecom.support@dalsemi.com or in Application Note 324, which is available at www.maxim-ic.com/AN324. The 1F capacitor in series with TTIPn is only necessary for G.703 clock sync applications. The 560pF on TTIPn/TRINGn must be tuned to your application. 81 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.1 LIU Operation The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer coupled into the RTIPn and RRINGn pins of the DS26518. The user has the option to use internal termination, software selectable for 75/100/110/120 applications, or external termination. The LIU recovers clock and data from the analog signal and passes it through the jitter attenuation mux. The DS26518 contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The receive circuitry also is configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input to the transmit side of the LIU is sent via the jitter attenuation mux to the wave shaping circuitry and line driver. The DS26518 will drive the E1 or T1 line from the TTIPn and TRINGn pins via a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1. The registers that control the LIU operation are shown in Table 9-38. Table 9-38. Registers Related to Control of the LIU REGISTER Global Transceiver Control Register 3 (GTCR3) Global Transceiver Clock Control Register 1 (GTCCR1) Global LIU Software Reset Register 1 (GSRR1) Global LIU Interrupt Status Register 1 (GLISR1) Global LIU Interrupt Mask Register 1 (GLIMR1) LIU Transmit Receive Control Register (LTRCR) LIU Transmit Impedance and Pulse Shape Selection Register (LTIPSR) LIU Maintenance Control Register (LMCR) LIU Real Status Register (LRSR) LIU Status Interrupt Mask Register (LSIMR) LIU Latched Status Register (LLSR) LIU Receive Signal Level Register (LRSL) LIU Receive Impedance and Sensitivity Monitor Register (LRISMR) FRAMER 1 ADDRESSES 00F2h 00F3h 00F6h 00FBh 00FEh 1000h 1001h 1002h 1003h 1004h 1005h 1006h 1007h FUNCTION Global transceiver control. MPS selections, backplane clock selections. Software reset control for the LIU. Interrupt status bit for each of the eight LIUs. Interrupt mask register for the LIU. T1/J1/E1 selection, output tri-state, loss criteria. Transmit pulse shape and impedance selection. Transmit maintenance and jitter attenuation control register. LIU real-time status register. LIU mask registers based on latched status bits. LIU latched status bits related to loss, open circuit, etc. LIU receive signal level indicator. LIU impedance match and sensitivity monitor. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8. 82 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.2 Transmitter NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data passes through a jitter attenuator if it is enabled for the transmit path. A digital sequencer and DAC are used to generate transmit waveforms compliant with T1.102 and G.703 pulse templates. A line driver is used to drive an internal matched impedance circuit for provision of 75, 100, 110, and 120 terminations. The transmitter couples to the E1 or T1 transmit twisted pair (or coaxial cable in some E1 applications) via a 1:2 step-up transformer. In order for the device to create the proper waveforms, the transformer used must meet the specifications listed in Table 9-40. The transmitter requires a transmit clock of 2.048MHz for E1 or 1.544MHz for T1/J1 operation. The DS26518 drivers have a short-circuit and open-circuit detection driver-fail monitor. The TXENABLE pin can high impedance the transmitter outputs for protection switching. The individual transmitters can also be placed in high impedance through register settings. The DS26518 also has functionality for powering down the transmitters individually. The relevant telecommunications specification compliance is shown in Table 9-39. Table 9-39. Telecommunications Specification Compliance for DS26518 Transmitters TRANSMITTER FUNCTION T1 Telecom Pulse Template Compliance T1 Telecom Pulse Template Compliance Transmit Electrical Characteristics for E1 Transmission and Return Loss Compliance TELECOMMUNICATIONS COMPLIANCE ANSI T1.403 ANSI T1.102 ITU-T G.703 Table 9-40. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Primary (Device Side) Transmit Transformer DC Resistance Secondary Primary (Device Side) Receive Transformer DC Resistance Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) 2% 600H minimum 1.0H maximum 40pF maximum 1.0 maximum 2.0 maximum 1.2 maximum 1.2 maximum 83 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.2.1 Transmit-Line Pulse Shapes The DS26518 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The T1/J1 pulse template is shown in Figure 9-20. The E1 pulse template is shown in Figure 9-21. The transmit pulse shape can be configured for each LIU on an individual basis. The LIU transmit impedance selection registers can be used to select an internal transmit terminating impedance of 100 for T1, 110 for J1 mode, 75 or 120 for E1 mode or no internal termination for E1 or T1 mode. The transmit pulse shape and terminating impedance is selected by LTIPSR registers. The pulse shapes will be compliant to T1.102 and G.703. Pulse shapes are measured for compliance at the appropriate network interface (NI). For T1 long haul and E1, the pulse shape is measured at the far end. For T1 short haul, the pulse shape is measured at the near end. Figure 9-20. T1/J1 Transmit Pulse Templates 1.2 1.1 1.0 0.9 0.8 0.7 NORMALIZED AMPLITUDE 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -500 -400 -300 -200 -100 0 100 200 TIME (ns) 300 400 500 600 700 T1.102/87, T1.403, CB 119 (Oct. 79), & I.431 Template DSX-1 Template (per ANSI T1.102 1993) MINIMUM CURVE MAXIMUM CURVE UI -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 Time -500 -255 -175 -175 -75 0 175 225 600 750 Amp. 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 UI -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 Time -500 -150 -150 -100 0 100 150 150 300 430 600 750 Amp. -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 DS1 Template (per ANSI T1.403 1995) MAXIMUM CURVE UI Time Amp. -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.34 0.77 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.20 1.20 1.05 1.05 -0.05 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.61 0.93 1.16 MINIMUM CURVE UI Time Amp. -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.26 -0.05 -0.05 84 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-21. E1 Transmit Pulse Templates 1.2 1.1 1.0 (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 269ns 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 219ns 194ns SCALED AMPLITUDE G.703 Template TIME (ns) 85 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.2.2 Transmit G.703 Section 10 Synchronization Signal The DS26518 can transmit a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T G.703. To use this mode, set the transmit G.703 synchronization clock bit (TG703) found in the LIU Transmit Impedance and Pulse Shape Selection Register (LTIPSR). This mode also requires a 1F blocking capacitor between TTIPn and the transformer. Additionally, the following registers should set to center the pulse to meet the pulse template: If configuring for E1 75 mode, set register address 0x1229 = 0xF8. If configuring for E1 120 mode, set register addresses 0x1229 = 0xF8 and 0x122D = 0x09. 9.12.2.3 Transmit Power-Down The individual transmitters can be powered down by setting the TPDE bit in the LIU Maintenance Control Register (LMCR). Note that powering down the transmit LIU results in a high-impedance state for the corresponding TTIPn and TRINGn pins. When transmit all ones (AIS) is invoked, continuous ones are transmitted using MCLK as the timing reference. Data input from the framer is ignored. AIS can be sent by setting a bit in the LMCR register. Transmit all ones will also be sent if the corresponding receiver goes into LOS state and the ATAIS bit is set in the LMCRl register. 9.12.2.4 Transmit Short-Circuit Detector/Limiter Each transmitter has an automatic short-circuit current limiter that activates when the load resistance is approximately 25 or less. TSCS (LRSR.2) provides a real-time indication of when the current limiter is activated. The LIU Latched Status Register (LLSR) provides latched versions of the information, which can be used to activate an interrupt when enable via the LSIMR register. 9.12.2.5 Transmit Open-Circuit Detector The DS26518 can also detect when the TTIPn or TRINGn outputs are open circuited. OCS (LRSR.1) will provide a real-time indication of when an open circuit is detected. Register LLSR provides latched versions of the information, which can be used to activate an interrupt when enabled via the LSIMR register. The open-circuit-detect feature is not available in T1 CSU operating modes (LBO 5, LBO 6, and LBO 7). 9.12.3 Receiver 9.12.3.1 Receive Internal Termination The DS26518 contains eight receivers. The termination circuit provides an analog switch that powers up in the open setting, providing high impedance to the receive line side. This is useful for redundancy applications and hot swapability. Three termination methods are available: * * * Partially internal impedance match with 120 external resistor. Fully internal impedance match, no external resistor. External resistor termination, internal termination disabled. See the LRISMR register for more details. Internal impedance match is configurable to 75, 100, 110, or 120 termination by setting the appropriate RIMPM[1:0] bits. These bits must be configured to match line impedance even if internal termination is disabled. Figure 9-22 shows a diagram of the switch control of termination. If internal impedance match is disabled, the external resistor, RT, must match the line impedance. 86 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 9-22. Receive LIU Termination Options LRISMR.RIMPON RECEIVE LIU TFR RTIPn 1:1 Rx LINE RT RT RRINGn The device couples to the receive E1 or T1 twisted pair (or coaxial cable in 75 E1 applications) via a 1:1 or 2:1 transformer. See Table 9-40 for transformer details. Receive sensitivity is configurable by setting the appropriate RSMS[1:0] bits (LRCR). The DS26518 uses a digital clock recovery system. The resultant E1, T1 or J1 clock derived from MCLK is multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding performance to meet jitter tolerance specifications shown in Figure 9-25. Normally, the clock that is output at the RCLKn pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS waveform presented at the RTIPn and RRINGn inputs. If the jitter attenuator (LTRCR) is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLKn to an approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLKn output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-sampled digital clock recovery circuitry. See Table 13-3 for more details. When no signal is present at RTIPn and RRINGn, a receive carrier loss (RCL) condition will occur and the RCLKn will be derived from the MCLKT1 or MCLKE1 source (depending on the configuration). 9.12.3.2 Receive Level Indicator The DS26518 will report the signal strength at RTIPn and RRINGn in approximately 2.5dB increments via RSL[3:0] located in the LIU Receive Signal Level Register (LRSL). This feature is helpful when trouble shooting line performance problems. 9.12.3.3 Receive G.703 Section 10 Synchronization Signal The DS26518 can receive a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T G.703. To use this mode, set the receive G.703 clock bit (RG703) found in the LIU Receive Control Register (LRCR.7). 87 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.3.4 Receiver Monitor Mode The receive equalizer is equipped with a monitor mode function that is used to overcome the signal attenuation caused by the resistive bridge used in monitoring applications. This function allows for a resistive gain of up to 32dB along with cable attenuation of 12dB to 30dB as shown in the LIU Receive Control Register (LRCR). Figure 9-23. Typical Monitor Application T1/E1 LINE PRIMARY T1/E1 TERMINATING DEVICE Rm X F M R Rm Rt DS2651x MONITOR PORT JACK SECONDARY T1/E1 TERMINATING DEVICE 9.12.3.5 Loss of Signal The DS26518 uses both the digital and analog loss-detection method in compliance with the latest T1.231 for T1/J1 and ITU-T G.775 or ETS 300 233 for E1 mode of operation. LOS is detected if the receiver level falls bellow a threshold analog voltage for certain duration. Alternatively, this can be termed as having received "zeros" for a certain duration. The signal level and timing duration are defined in accordance with the T1.231 or G.775 or ETS 300 233 specifications. For short-haul mode, the loss-detection thresholds are based on cable loss of 12dB to 18dB for both T1/J1 and E1 modes. The loss thresholds are selectable based on Table 10-20. For long-haul mode, the LOS-detection threshold is based on cable loss of 30dB to 38dB for T1/J1 and 30dB to 45dB for E1 mode. Note there is no explicit bit called short-haul mode selection. Loss declaration level is set at 3dB lower than the maximum sensitivity setting programmed in Table 10-20. The loss state is exited when the receiver detects a certain ones density at the maximum sensitivity level or higher, which is 3dB higher than the loss-detection level. The loss-detection signal level and loss-reset signal level are defined with hysteresis to prevent the receiver from bouncing between "LOS" and "no LOS" states. Table 9-41 outlines the specifications governing the loss function. 88 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 9-41. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications CRITERIA Loss Detection T1.231 No pulses are detected for 175 75 bits. Loss is terminated if a duration of 12.5% ones are detected over duration of 175 75 bits. Loss is not terminated if 8 consecutive zeros are found if B8ZS encoding is used. If B8ZS is not used, loss is not terminated if 100 consecutive pulses are zero. STANDARD ITU-T G.775 No pulses are detected for duration of 10 to 255 bit periods. The incoming signal has transitions for duration of 10 to 255 bit periods. ETS 300 233 No pulses are detected for a duration of 2048 bit periods or 1ms. Loss reset criteria is not defined. Loss Reset 9.12.3.6 ANSI T1.231 for T1 and J1 Modes For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 10-20) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss is declared at 15dB. LOS is reset if all the following crieria are met: 1) 24 or more ones are detected in a 192-bit period with a programmed sensitivity level measured at RTIPn and RRINGn. 2) During the 192 bits, fewer than 100 consecutive zeros are detected. For long-haul mode, loss is detected if the received signal level is 3dB lower from the programmed value (based on Table 10-20) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 30dB, the loss declaration level is 33dB. LOS is reset if all the following crieria are met: 1) 24 or more ones are detected in a 192-bit period with a programmed sensitivity level measured at RTIPn and RRINGn. 2) During the 192 bits, fewer than 100 consecutive zeros are detected. 9.12.3.7 ITU-T G.775 for E1 Modes For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 10-20) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss is declared at 15dB. LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for a duration of 192-bit periods. For long-haul mode, loss is detected if the received signal level is 3dB lower from the programmed value (based on Table 10-20) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 30dB, the loss declaration level is 15dB. LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for a duration of 192-bit periods. 9.12.3.8 ETS 200 233 for E1 Modes For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 10-20) continusou duration of 2048-bit periods (1ms). LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for a duration of 192-bit periods. For long-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 10-20) continuous duration of 2048-bit periods (1ms). LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for a duration of 192-bit periods. 89 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.4 Hitless Protection Switching (HPS) Many current redundancy protection implementations use mechanical relays to switch between primary and backup boards. The switching time in relays is typically in the milliseconds, making T1/E1 HPS impossible. The switching event will likely cause frame-synchronization loss in any equipment downstream, affecting the quality of service. The same is also true for tri-stating mechanisms that use software or inactive clocks for the triggering of HPS. The DS26518 LIUs feature fast tristatable outputs for TTIPn and TRINGn and fast disabling of internal impedance matching for RTIPn and RRINGn within one-bit period. The TXENABLE pin is used for hitless protection circuits in combination with the LTRCR.RHPM bit. When low, the TXENABLE pin tri-states all eight transmitters, providing a high-impedance state on TTIPn and TRINGn. If the RHPM bit is set, the TXENABLE pin, when low, will also disable the internal termination on RTIPn and RRINGn on a per-port basis, providing a high impedance to the receive line. This is a very useful function in that control can be done through a hardware pin, allowing a quick switch to the backup system for both the receiver and the transmitter. Figure 9-24 shows a typical HPS application. Figure 9-24. HPS Block Diagram RTIP RRING PRIMARY BOARD TXENABLE TTIP TRING RX SWITCHING CONTROL LINE INTERFACE CARD TX RTIP TXENABLE RRING BACKUP BOARD TTIP TRING 90 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.5 Jitter Attenuator The DS26518 contains a jitter attenuator that can be set to a depth of 32 or 128 bits via the JADS bits in LIU Transmit and Receive Control Register (LTRCR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation are shown in Figure 9-25. The jitter attenuator can be placed in either the receive path or the transmit path, or be disabled by appropriately setting the JAPS1 and JAPS0 bits in the LIU Transmit and Receive Control Register (LTRCR). For the jitter attenuator to operate properly, a 2.048MHz, 1.544MHz, or a multiple of up to 8x clock must be applied at MCLK. See the Global Transceiver Clock Control Register 1 (GTCCR1) for MCLK options. ITU-T specification G.703 requires an accuracy of 50ppm for both T1/J1 and E1 applications. TR62411 and ANSI specs require an accuracy of 32ppm for T1/J1 interfaces. Circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLKn pin to create a smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKn pin if the jitter attenuator is placed in the transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128-bits) or 28UIP-P (buffer depth is 32 bits), then the DS26518 will set the jitter attenuator limit trip (JALTS) bit in the LIU Latched Status Register (LLSR.3). In T1/J1 mode, the jitter attenuator corner frequency is 3.75Hz, and in E1 mode it is 0.6Hz. The DS26518 jitter attenuator is compliant with the following specifications shown in Table 9-42. Table 9-42. Jitter Attenuator Standards Compliance Standard ITU-T I.431, G.703, G.736, G.823 ETS 300 011, TBR 12/13 AT&T TR62411, TR43802 TR-TSY 009, TR-TSY 253, TR-TSY 499 Figure 9-25. Jitter Attenuation 0dB TBR12 Prohibited Area ITU G.7XX Prohibited Area JITTER ATTENUATION (dB) -20dB C ve ur A E1 T1 -40dB Cu rve B TR 62411 (Dec. 90) Prohibited Area -60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K 91 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.6 LIU Loopbacks The DS26518 provides four LIU loopbacks for diagnostic purposes: Analog Loopback, Local Loopback, Remote Loopback 1, and Remote Loopback 2. Dual Loopback is a combination of Local Loopback and Remote Loopback 1. In the loopback diagrams that follow, TSERn, TCLKn, RSERn, and RCLKn are inputs/outputs from the framer. Figure 9-26. Loopback Diagram MCLK Master Clock PLL JACLK RTIP RRING RX LIU Jitter Attenuator (in RX path) RX FRAMER RCLK RSER Jitter Attenuator can be assigned to receive path or transmit path or disabled Jitter Attenuator (in TX path) Remote 1 Loopback Remote 2 Loopback Analog Loopback Local Loopback TTIP TRING TX LIU TX FORMATTER TCLK TSER 9.12.6.1 Analog Loopback The analog output of the transmitter TTIPn and TRINGn is looped back to RTIPn and RRINGn of the receiver. Data at RTIPn and RRINGn is ignored in analog loopback. This is shown in the Figure 9-27. Figure 9-27. Analog Loopback TTIP TCLK TSER Transmit Framer Optional Jitter Attenuator Transmit Digital Transmit Analog Line Driver TRING RCLK RSER Receive Framer Optional Jitter Attenuator Receive Digital Receive Analog RTIP RRING 92 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.6.2 Local Loopback The transmit system data is looped back to the receive framer. This data is also encoded and output on TTIPn and TRINGn. Signals at RTIPn and RRINGn are ignored. This loopback is conceptually shown in Figure 9-28. Figure 9-28. Local Loopback TCLK TSER Transmit Framer Optional Jitter Attenuator Transmit Digital Transmit Analog TTIP Line Driver TRING RCLK RSER Receive Framer Optional Jitter Attenuator Receive Digital Receive Analog RTIP RRING 9.12.6.3 Remote Loopback 1 The outputs decoded from the receive LIU are looped back to the transmit LIU, not including the jitter attenuator in the path. Remote Loopback 2 includes the jitter attenuator in the loopback path. The inputs from the transmit framer are ignored during Remote Loopback 1. 9.12.6.4 Remote Loopback 2 The outputs decoded from the receive LIU are looped back to the transmit LIU, including the jitter attenuator. The inputs from the transmit framer are ignored during Remote Loopback 2. This loopback is conceptually shown in Figure 9-29. Figure 9-29. Remote Loopback 2 TCLK TSER Transmit Framer Optional Jitter Attenuator Transmit Digital Transmit Analog TTIP Line Driver TRING RCLK RSER Receive Framer Optional Jitter Attenuator Receive Digital Receive Analog RTIP RRING 93 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.12.6.5 Dual Loopback The inputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer are looped back to the receiver with the optional jitter attenuator. Dual Loopback is a combination of Local Loopback and Remote Loopback 1. This loopback is invoked by setting the correct bits in the LIU Maintenance Control Register (LMCR). This loopback is conceptually shown in Figure 9-30. Figure 9-30. Dual Loopback TTIP Transmit Framer Optional Jitter Attenuator Transmit Digital Transmit Analog TCLK TSER Line Driver TRING RCLK RSER Receive Framer Optional Jitter Attenuator Receive Digital Receive Analog RTIP RRING 94 of 286 DS26518 8-Port T1/E1/J1 Transceiver 9.13 Bit Error-Rate Test Function (BERT) The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating bit patterns. It is used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers. The registers related to the configure, control, and status of the BERT are shown in Table 9-43. Table 9-43. Registers Related to Configure, Control, and Status of BERT REGISTER Global BERT Interrupt Status Register 1 (GBISR1) Global BERT Interrupt Mask Register 1 (GBIMR1) Receive Expansion Port Control Register (RXPC) Receive BERT Port Bit Suppress Register (RBPBS) Receive BERT Port Channel Select Registers 1 to 4 (RBPCS1-4) Transmit Expansion Port Control Register (TXPC) Transmit BERT Port Bit Suppress Register (TBPBS) Transmit BERT Port Channel Select Registers 1 to 4 (TBPCS1-4) BERT Alternating Word Count Rate Register (BAWC) BERT Repetitive Pattern Set Register 1 (BRP1) BERT Repetitive Pattern Set Register 2 (BRP2) BERT Repetitive Pattern Set Register 3 (BRP3) BERT Repetitive Pattern Set Register 4 (BRP4) BERT Control Register 1 (BC1) BERT Control Register 2 (BC2) BERT Bit Count Register 1 (BBC1) BERT Bit Count Register 2 (BBC2) BERT Bit Count Register 3 (BBC3) BERT Bit Count Register 4 (BBC4) BERT Error Count Register 1 (BEC1) BERT Error Count Register 2 (BEC2) BERT Error Count Register 3 (BEC3) BERT Latched Status Register (BLSR) BERT Status Interrupt Mask Register (BSIM) FRAMER 1 ADDRESSES 00FAh 00FDh 08Ah 08Bh 0D4h, 0D5h, 0D6h, 0D7h 18Ah 18Bh 1D4h, 1D5h, 1D6h, 1D7h 1100h 1101h 1102h 1103h 1104h 1105h 1106h 1107h 1108h 1109h 110Ah 110Bh 110Ch 110Dh 110Eh 110Fh FUNCTION When any of the 8 BERTs issue an interrupt, a bit will be set. When any of the 8 BERTs issue an interrupt, a bit will be set. Enable for the receiver BERT. Bit suppression for the receive BERT. Channels to be enabled for the Framer to accept data from the BERT pattern generator Enable for the transmitter BERT. Bit suppression for the transmit BERT. Channels to be enabled for the framer to accept data from the transmit BERT pattern generator. BERT alternating pattern count register. BERT repetitive pattern set register 1. BERT repetitive pattern set register 2. BERT repetitive pattern set register 3. BERT repetitive pattern set register 4. Pattern selection and misc control BERT bit pattern length control Increments for BERT bit clocks. BERT bit counter. BERT bit counter. BERT bit counter. BERT error counter. BERT error counter. BERT error counter. Denotes synchronization loss and other status. BERT interrupt mask. Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer N = (Framer 1 address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8. 95 of 286 DS26518 8-Port T1/E1/J1 Transceiver The BERT block can generate and detect the following patterns: * The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS. * A repetitive pattern from 1 to 32 bits in length. * Alternating (16-bit) words that flip every 1 to 256 words. * Daly pattern. The BERT function must be enabled and configured in the TXPC and RXPC registers for each port. The BERT can then be assigned on a per-channel basis for both the transmitter and receiver, using the special per-channel function in the TBPCS1-4 and RBCS1-4 registers. Individual bit positions within the channels can be suppressed with the TBPBS and RBPBS registers. Using combinations of these functions, the BERT pattern can be transmitted and/or received in single or across multiple DS0s, contiguous or broken. Transmit and receive bandwidth assignments are independent of each other. The BERT receiver has a 32-bit bit counter and a 24-bit error counter. The BERT receiver can generate interrupts on: a change in receive-synchronizer status, receive all zeros, receive all ones, error counter overflow, bit counter overflow, and bit error detection. Interrupts from each of these events can be masked within the BERT function via the BERT Status Interrupt Mask Register (BSIM). If the software detects that the BERT has reported an event, then the software must read the BERT Latched Status Register (BLSR) to determine which event(s) has occurred. 9.13.1 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern was the repeating 5-bit pattern ...01101... (where the rightmost bit is the one sent first and received first), then BRP1 should be loaded with ADh, BRP2 with B5h, BRP3 with D6h, and BRP4 should be loaded with 5Ah. For a pseudo-random pattern, all four registers should be loaded with all ones (i.e., FFh). For an alternating word pattern, one word should be placed into BRP1 and BRP2 and the other word should be placed into BRP3 and BRP4. For example, if the DDS stress pattern "7E" is to be described, the user would place 00h in BRP1, 00h in BRP2, 7Eh in BRP3, and 7Eh in BRP4, and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h followed by 100 bytes of 7Eh to be sent and received. 9.13.2 BERT Error Counter Once BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and will set the BECO status bit in the BLSR register. 96 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10. DEVICE REGISTERS Thirteen address bits are used to control the settings of the registers. The registers control functions of the framers, LIUs, and BERTs within the DS26518. The map is divided into eight framers, followed by eight LIUs and eight BERTs. Global registers (applicable to all eight transceivers and BERTs) are located within the address space of Framer 1. The register details are provided in the following tables. The framer registers bits are provided for Framer 1 and address bits A[12:8] determine the framer addressed. 10.1 Register Listings The framer registers have an offset of 200 hex, the LIU registers have an offset of 20 hex, and the BERT registers have an offset of 10 hex for each transceiver. Table 10-1. Register Address Ranges (in Hex) CHANNEL -- CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 GLOBAL 00F0-00FF -- -- -- -- -- -- -- -- RECEIVE FRAMER -- 0000-00EF 0200-02EF 0400-04EF 0600-06EF 0800-08EF 0A00-0AEF 0C00-0CEF 0E00-0EEF TRANSMIT FRAMER -- 0100-01EF 0300-03EF 0500-05EF 0700-07EF 0900-09EF 0B00-0BEF 0D00-0DEF 0F00-0FEF LIU -- 1000-101F 1020-103F 1040-105F 1060-107F 1080-109F 10A0-10BF 10C0-10DF 10E0-10FF BERT -- 1100-110F 1110-111F 1120-112F 1130-113F 1140-114F 1150-115F 1160-116F 1170-117F 97 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.1.1 Global Register List Table 10-2. Global Register List GLOBAL REGISTER LIST ADDRESS 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh Note 1: Note 2: NAME GTCR1 GFCR1 GTCR3 GTCCR1 GTCCR3 -- GSRR1 -- IDR GFISR1 GBISR1 GLISR1 GFIMR1 GBIMR1 GLIMR1 DESCRIPTION Global Transceiver Control Register 1 Global Framer Control Register 1 Global Transceiver Control Register 3 Global Transceiver Clock Control Register 1 Global Transceiver Clock Control Register 3 Reserved Global LIU Software Reset Register 1 Reserved Device Identification Register Global Framer Interrupt Status Register 1 Global BERT Interrupt Status Register 1 Global LIU Interrupt Status Register 1 Global Framers Interrupt Mask Register 1 Global BERT Interrupt Mask Register 1 Global LIU Interrupt Mask Register 1 R/W R/W R/W R/W R/W R/W -- R/W -- R R R R RW RW RW Reserved registers should only be written with all zeros. The global registers are located in the framer address space. The corresponding address space for the other seven framers is "Reserved," and should be initialized with all zeros for proper operation. 98 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.1.2 Framer Register List Table 10-3. Framer Register List Note that only Framer 1 address is presented here. The same set of registers definitions applies for transceivers 2 to 8 in accordance with the DS26518 map offsets. Transceiver offset is [(n - 1) x 200 hex], where n designates the transceiver in question. FRAMER REGISTER LIST ADDRESS 000h 001h 002h 003h 004h-00Fh 010h 011h 012h 013h 014h 015h 016h-01Fh 020h 021h 022h 023h 024h 025h 026h 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 02Fh 030h 031h 032h 033h 034h 035h 036h 037h 038h 039h 03Ah 03B 03C 03Dh NAME E1RDMWE1 E1RDMWE2 E1RDMWE3 E1RDMWE4 -- RHC RHBSE RDS0SEL RSIGC T1RCR2 E1RSAIMR T1RBOCC -- RIDR1 RIDR2 RIDR3 RIDR4 RIDR5 RIDR6 RIDR7 RIDR8 RIDR9 RIDR10 RIDR11 RIDR12 RIDR13 RIDR14 RIDR15 RIDR16 RIDR17 RIDR18 RIDR19 RIDR20 RIDR21 RIDR22 RIDR23 RIDR24 T1RSAOI1 RIDR25 T1RSAOI2 RIDR26 T1RSAOI3 RIDR27 RIDR28 T1RDMWE1 RIDR29 T1RDMWE2 DESCRIPTION E1 Receive Digital Milliwatt Enable Register 1 E1 Receive Digital Milliwatt Enable Register 2 E1 Receive Digital Milliwatt Enable Register 3 E1 Receive Digital Milliwatt Enable Register 4 Reserved Receive HDLC Control Register Receive HDLC Bit Suppress Register Receive Channel Monitor Select Register Receive-Signaling Control Register Receive Control Register 2 (T1 Mode) Receive Sa-Bit Interrupt Mask Register (E1 Mode) Receive BOC Control Register (T1 Mode Only) Reserved Receive Idle Code Definition Register 1 Receive Idle Code Definition Register 2 Receive Idle Code Definition Register 3 Receive Idle Code Definition Register 4 Receive Idle Code Definition Register 5 Receive Idle Code Definition Register 6 Receive Idle Code Definition Register 7 Receive Idle Code Definition Register 8 Receive Idle Code Definition Register 9 Receive Idle Code Definition Register 10 Receive Idle Code Definition Register 11 Receive Idle Code Definition Register 12 Receive Idle Code Definition Register 13 Receive Idle Code Definition Register 14 Receive Idle Code Definition Register 15 Receive Idle Code Definition Register 16 Receive Idle Code Definition Register 17 Receive Idle Code Definition Register 18 Receive Idle Code Definition Register 19 Receive Idle Code Definition Register 20 Receive Idle Code Definition Register 21 Receive Idle Code Definition Register 22 Receive Idle Code Definition Register 23 Receive Idle Code Definition Register 24 Receive-Signaling All-Ones Insertion Register 1 (T1 Mode Only) Receive Idle Code Definition Register 25 (E1 Mode) Receive-Signaling All-Ones Insertion Register 2 (T1 Mode Only) Receive Idle Code Definition Register 26 (E1 Mode) Receive-Signaling All-Ones Insertion Register 3 (T1 Mode Only) Receive Idle Code Definition Register 27 (E1 Mode) Receive Idle Code Definition Register 28 (E1 Mode) T1 Receive Digital Milliwatt Enable Register 1 (T1 Mode Only) Receive Idle Code Definition Register 29 (E1 Mode) T1 Receive Digital Milliwatt Enable Register 2 (T1 Mode Only) 99 of 286 R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS 03Eh 03Fh 040h 041h 042h 043h 044h 045h 046h 047h 048h 049h 04Ah 04Bh 04Ch 04Dh 04Eh 04Fh 050h 051h 052h 053h 054h 055h 056h 057h 058h 059h 05Ah 05Bh 060h 061h 062h 063h 064h 065h 066h 067h 068h 069h 06Ah 06Bh 06Ch 06Dh 06Eh 06Fh 070h-07Fh NAME RIDR30 T1RDMWE3 RIDR31 RIDR32 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 E1EBCR1 E1EBCR2 FEACR1 FEACR2 FEBCR1 FEBCR2 RDS0M -- T1RFDL E1RRTS7 T1RBOC T1RSLC1 E1RAF T1RSLC2 E1RNAF T1RSLC3 E1RsiAF E1RSiNAF E1RRA E1RSa4 E1RSa5 E1RSa6 E1RSa7 E1RSa8 SaBITS Sa6CODE -- DESCRIPTION Receive Idle Code Definition Register 30 (E1 Mode) T1 Receive Digital Milliwatt Enable Register 3 (T1 Mode Only) Receive Idle Code Definition Register 31 (E1 Mode) Receive Idle Code Definition Register 32 (E1 Mode) Receive-Signaling Register 1 Receive-Signaling Register 2 Receive-Signaling Register 3 Receive-Signaling Register 4 Receive-Signaling Register 5 Receive-Signaling Register 6 Receive-Signaling Register 7 Receive-Signaling Register 8 Receive-Signaling Register 9 Receive-Signaling Register 10 Receive-Signaling Register 11 Receive-Signaling Register 12 Receive-Signaling Register 13 (E1 Mode only) Receive-Signaling Register 14 (E1 Mode only) Receive-Signaling Register 15 (E1 Mode only) Receive-Signaling Register 16 (E1 Mode only) Line Code Violation Count Register 1 Line Code Violation Count Register 2 Path Code Violation Count Register 1 Path Code Violation Count Register 2 Frames Out of Sync Count Register 1 Frames Out of Sync Count Register 2 E-Bit Count 1 (E1 Mode Only) E-Bit Count 2 (E1 Mode Only) Error Count A Register 1 Error Count A Register 2 Error Count B Register 1 Error Count B Register 2 Receive DS0 Monitor Register Reserved Receive FDL Register (T1 Mode) Receive Real-Time Status Register 7 (E1 Mode) Receive BOC Register (T1 Mode) Receive SLC-96 Data Link Register 1 (T1 Mode) E1 Receive Align Frame Register (E1 Mode) Receive SLC-96 Data Link Register 2 (T1 Mode) E1 Receive Non-Align Frame Register (E1 Mode) Receive SLC-96 Data Link Register 3 (T1 Mode) E1 Received Si Bits of the Align Frame Register (E1 Mode) Received Si Bits of the Non-Align Frame Register (E1 Mode) Received Remote Alarm Register (E1 Mode) E1 Receive Sa4 Bits Register (E1 Mode Only) E1 Receive Sa5 Bits Register (E1 Mode Only) E1 Receive Sa6 Bits Register (E1 Mode Only) E1 Receive Sa7 Bits Register (E1 Mode Only) Receive Sa8 Bits Register (E1 Mode Only) E1 Receive SaX Bits Register Received Sa6 Codeword Register Reserved 100 of 286 R/W R/W -- R R R R R R R R R R R R -- -- -- -- R R R R R R R R R/W R/W R/W R/W R -- R R R R R R R R R R R R R R -- DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08B 08Ch-08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h 0A1h 0A2h 0A3h 0A4h 0A5h 0A6h 0A7h 0A8h 0A9h 0AAh 0ABh 0ACh 0ADh 0AEh 0AFh 0B0h NAME RMMR RCR1 RCR1 T1RIBCC E1RCR2 RCR3 RIOCR RESCR ERCNT RHFC RIBOC T1RSCC RXPC RBPBS -- RLS1 RLS2 RLS2 RLS3 RLS3 RLS4 RLS5 -- RLS7 RLS7 -- RSS1 RSS2 RSS3 RSS4 T1RSCD1 T1RSCD2 -- RIIR RIM1 RIM2 RIM3 RIM3 RIM4 RIM5 -- RIM7 RIM7 -- RSCSE1 RSCSE2 RSCSE3 RSCSE4 T1RUPCD1 T1RUPCD2 T1RDNCD1 T1RDNCD2 RRTS1 DESCRIPTION Receive Master Mode Register Receive Control Register 1 (T1 Mode) Receive Control Register 1 (E1 Mode) Receive In-Band Code Control Register (T1 Mode) Receive Control Register 2 (E1 Mode) Receive Control Register 3 Receive I/O Configuration Register Receive Elastic Store Control Register Error-Counter Configuration Register Receive HDLC FIFO Control Register Receive Interleave Bus Operation Control Register In-Band Receive Spare Control Register (T1 Mode Only) Receive Expansion Port Control Register Receive BERT Port Bit Suppress Register Reserved Receive Latched Status Register 1 Receive Latched Status Register 2 (T1 Mode) Receive Latched Status Register 2 (E1 Mode) Receive Latched Status Register 3 (T1 Mode) Receive Latched Status Register 3 (E1 Mode) Receive Latched Status Register 4 Receive Latched Status Register 5 (HDLC) Reserved Receive Latched Status Register 7 (T1 Mode) Receive Latched Status Register 7 (E1 Mode) Reserved Receive-Signaling Status Register 1 Receive-Signaling Status Register 2 Receive-Signaling Status Register 3 Receive-Signaling Status Register 4 (E1 Mode Only) Receive Spare Code Definition Register 1 (T1 Mode Only) Receive Spare Code Definition Register 2 (T1 Mode Only) Reserved Receive Interrupt Information Register Receive Interrupt Mask Register 1 Receive Interrupt Mask Register 2 (E1 Mode Only) Receive Interrupt Mask Register 3 (T1 Mode) Receive Interrupt Mask Register 3 (E1 Mode) Receive Interrupt Mask Register 4 Receive Interrupt Mask Register 5 (HDLC) Reserved Receive Interrupt Mask Register 7 (BOC:FDL) (T1 Mode) Receive Interrupt Mask Register 7 (BOC:FDL) (E1 Mode) Reserved Receive-Signaling Change of State Enable Register 1 Receive-Signaling Change of State Enable Register 2 Receive-Signaling Change of State Enable Register 3 Receive-Signaling Change of State Enable Register 4 (E1 Mode Only) Receive Up Code Definition Register 1 (T1 Mode Only) Receive Up Code Definition Register 2 (T1 Mode Only) Receive Down Code Definition Register 1 (T1 Mode Only) Receive Down Code Definition Register 2 (T1 Mode Only) Receive Real-Time Status Register 1 101 of 286 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W -- R/W -- R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W -- R/W -- R/W R/W R/W -- R/W R/W R/W R/W R DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS 0B1h 0B2h 0B3h 0B4h 0B5h 0B6h 0B7h-0BFh 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h 0C9h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0D8h-0EFh 0F0h-0FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 110h 111h 112h 113h 114h 115h-117h NAME -- RRTS3 RRTS3 -- RRTS5 RHPBA RHF -- RBCS1 RBCS2 RBCS3 RBCS4 RCBR1 RCBR2 RCBR3 RCBR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 RCICE4 RBPCS1 RBPCS2 RBPCS3 RBPCS4 -- Global Registers (Section 10.3) TDMWE1 TDMWE2 TDMWE3 TDMWE4 TJBE1 TJBE2 TJBE3 TJBE4 TDDS1 TDDS2 TDDS3 THC1 THBSE -- THC2 E1TSACR -- DESCRIPTION Reserved Receive Real-Time Status Register 3 (T1 Mode) Receive Real-Time Status Register 3 (E1 Mode) Reserved Receive Real-Time Status Register 5 (HDLC) Receive HDLC Packet Bytes Available Register Receive HDLC FIFO Register Reserved Receive Blank Channel Select Register 1 Receive Blank Channel Select Register 2 Receive Blank Channel Select Register 3 Receive Blank Channel Select Register 4 (E1 Mode Only) Receive Channel Blocking Register 1 Receive Channel Blocking Register 2 Receive Channel Blocking Register 3 Receive Channel Blocking Register 4 (E1 Mode Only) Receive-Signaling Reinsertion Enable Register 1 Receive-Signaling Reinsertion Enable Register 2 Receive-Signaling Reinsertion Enable Register 3 Receive-Signaling Reinsertion Enable Register 4 (E1 Mode Only) Receive Gapped Clock Channel Select Register 1 Receive Gapped Clock Channel Select Register 2 Receive Gapped Clock Channel Select Register 3 Receive Gapped Clock Channel Select Register (E1 Mode Only) Receive Channel Idle Code Enable Register 1 Receive Channel Idle Code Enable Register 2 Receive Channel Idle Code Enable Register 3 Receive Channel Idle Code Enable Register 4 (E1 Mode Only) Receive BERT Port Channel Select Register 1 Receive BERT Port Channel Select Register 2 Receive BERT Port Channel Select Register 3 Receive BERT Port Channel Select Register 4 (E1 Mode Only) Reserved See the Global Register list in Table 10-2. Note that this space is "Reserved" in Framers 2 to 8. Transmit Digital Milliwatt Enable Register 1 (T1 and E1 Modes) Transmit Digital Milliwatt Enable Register 2 (T1 and E1 Modes) Transmit Digital Milliwatt Enable Register 3 (T1 and E1 Modes) Transmit Digital Milliwatt Enable Register 4 (T1 and E1 Modes) Transmit Jammed Bit Eight Stuffing Register 1 Transmit Jammed Bit Eight Stuffing Register 2 Transmit Jammed Bit Eight Stuffing Register 3 Transmit Jammed Bit Eight Stuffing Register 4 Transmit DDS Zero Code Register 1 Transmit DDS Zero Code Register 2 Transmit DDS Zero Code Register 3 Transmit HDLC Control Register 1 Transmit HDLC Bit Suppress Register Reserved Transmit HDLC Control Register 2 E1 Transmit Sa-Bit Control Register (E1 Mode) Reserved 102 of 286 R/W -- R -- R R R -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W -- DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS 118h 119h 11Ah 11Bh 11Ch-11Fh 120h 121h 122h 123h 124h 125h 126h 127h 128h 129h 12Ah 12Bh 12Ch 12Dh 12Eh 12Fh 130h 131h 132h 133h 134h 135h 136h 137h 138h 139h 13Ah 13Bh 13Ch 13Dh 13Eh 13Fh 140h 141h 142h 143h 144h 145h 146h 147h 148h 149h 14Ah 14Bh 14Ch 14Dh 14Eh 14Fh NAME SSIE1 SSIE2 SSIE3 SSIE4 -- TIDR1 TIDR2 TIDR3 TIDR4 TIDR5 TIDR6 TIDR7 TIDR8 TIDR9 TIDR10 TIDR11 TIDR12 TIDR13 TIDR14 TIDR15 TIDR16 TIDR17 TIDR18 TIDR19 TIDR20 TIDR21 TIDR22 TIDR23 TIDR24 TIDR25 TIDR26 TIDR27 TIDR28 TIDR29 TIDR30 TIDR31 TIDR32 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 DESCRIPTION Software-Signaling Insertion Enable Register 1 Software-Signaling Insertion Enable Register 2 Software-Signaling Insertion Enable Register 3 Software-Signaling Insertion Enable Register 4 (E1 Mode Only) Reserved Transmit Idle Code Definition Register 1 Transmit Idle Code Definition Register 2 Transmit Idle Code Definition Register 3 Transmit Idle Code Definition Register 4 Transmit Idle Code Definition Register 5 Transmit Idle Code Definition Register 6 Transmit Idle Code Definition Register 7 Transmit Idle Code Definition Register 8 Transmit Idle Code Definition Register 9 Transmit Idle Code Definition Register 10 Transmit Idle Code Definition Register 11 Transmit Idle Code Definition Register 12 Transmit Idle Code Definition Register 13 Transmit Idle Code Definition Register 14 Transmit Idle Code Definition Register 15 Transmit Idle Code Definition Register 16 Transmit Idle Code Definition Register 17 Transmit Idle Code Definition Register 18 Transmit Idle Code Definition Register 19 Transmit Idle Code Definition Register 20 Transmit Idle Code Definition Register 21 Transmit Idle Code Definition Register 22 Transmit Idle Code Definition Register 23 Transmit Idle Code Definition Register 24 Transmit Idle Code Definition Register 25 (E1 Mode Only) Transmit Idle Code Definition Register 26 (E1 Mode Only) Transmit Idle Code Definition Register 27 (E1 Mode Only) Transmit Idle Code Definition Register 28 (E1 Mode Only) Transmit Idle Code Definition Register 29 (E1 Mode Only) Transmit Idle Code Definition Register 30 (E1 Mode Only) Transmit Idle Code Definition Register 31 (E1 Mode Only) Transmit Idle Code Definition Register 32 (E1 Mode Only) Transmit-Signaling Register 1 Transmit-Signaling Register 2 Transmit-Signaling Register 3 Transmit-Signaling Register 4 Transmit-Signaling Register 5 Transmit-Signaling Register 6 Transmit-Signaling Register 7 Transmit-Signaling Register 8 Transmit-Signaling Register 9 Transmit-Signaling Register 10 Transmit-Signaling Register 11 Transmit-Signaling Register 12 Transmit-Signaling Register 13 Transmit-Signaling Register 14 Transmit-Signaling Register 15 Transmit-Signaling Register 16 103 of 286 R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS 150h 151h 152h 153h 154h-161h 162h 163h 164h 165h 166h 167h 168h 169h 16Ah 16Bh 16Ch 16Dh 16Eh-17Fh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch-18Dh 18Eh 18F 190h 191h 192h 193h-19Eh 19Fh 1A0h 1A1h 1A2h 1A3h-1ABh 1ACh 1ADh 1AEh-1B0h 1B1h 1B2h 1B3h NAME TCICE1 TCICE2 TCICE3 TCICE4 -- T1TFDL T1TBOC T1TSLC1 E1TAF T1TSLC2 E1TNAF T1TSLC3 E1TSiAF E1TSiNAF E1TRA E1TSa4 E1TSa5 E1TSa6 E1TSa7 E1TSa8 -- TMMR TCR1 TCR1 T1.TCR2 E1.TCR2 TCR3 TIOCR TESCR TCR4 THFC TIBOC TDS0SEL TXPC TBPBS -- TSYNCC -- TLS1 TLS2 TLS3 -- TIIR TIM1 TIM2 TIM3 -- T1TCD1 T1TCD2 -- TRTS2 -- TFBA DESCRIPTION Transmit Channel Idle Code Enable Register 1 Transmit Channel Idle Code Enable Register 2 Transmit Channel Idle Code Enable Register 3 Transmit Channel Idle Code Enable Register 4 (E1 Mode Only) Reserved Transmit FDL Register (T1 Mode Only) Transmit BOC Register (T1 Mode Only) Transmit SLC-96 Data Link Register 1 (T1 Mode) Transmit Align Frame Register (E1 Mode) Transmit SLC-96 Data Link Register 2 (T1 Mode) Transmit Non-Align Frame Register (E1 Mode) Transmit SLC-96 Data Link Register 3 (T1 Mode) Transmit Si Bits of the Align Frame Register (E1 Mode) Transmit Si Bits of the Non-Align Frame Register (E1 Mode Only) Transmit Remote Alarm Register (E1 Mode) Transmit Sa4 Bits Register (E1 Mode Only) Transmit Sa5 Bits Register (E1 Mode Only) Transmit Sa6 Bits Register (E1 Mode Only) Transmit Sa7 Bits Register (E1 Mode Only) Transmit Sa8 Bits Register (E1 Mode Only) Reserved Transmit Master Mode Register Transmit Control Register 1 (T1 Mode) Transmit Control Register 1 (E1 Mode) Transmit Control Register 2 (T1 Mode) Transmit Control Register 2 (E1 Mode) Transmit Control Register 3 Transmit I/O Configuration Register Transmit Elastic Store Control Register Transmit Control Register 4 (T1 Mode Only) Transmit HDLC FIFO Control Register Transmit Interleave Bus Operation Control Register Transmit DS0 Channel Monitor Select Register Transmit Expansion Port Control Register Transmit BERT Port Bit Suppress Register Reserved Transmit Synchronizer Control Register Reserved Transmit Latched Status Register 1 Transmit Latched Status Register 2 (HDLC) Transmit Latched Status Register 3 (Synchronizer) Reserved Transmit Interrupt Information Register Transmit Interrupt Mask Register 1 Transmit Interrupt Mask Register 2 (HDLC) Transmit Interrupt Mask Register 3 (Synchronizer) Reserved Transmit Code Definition Register 1 (T1 Mode Only) Transmit Code Definition Register 2 (T1 Mode Only) Reserved Transmit Real-Time Status Register 2 (HDLC) Reserved Transmit HDLC FIFO Buffer Available Register 104 of 286 R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W -- R/W R/W R/W -- R/W R/W R/W R/W -- R/W R/W -- R -- R DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS 1B4h 1B5h-1BhA 1BBh 1BCh-1BFh 1C0h 1C1h 1C2h 1C3h 1C4h 1C5h 1C6h 1C7h 1C8h 1C9h 1CAh 1CBh 1CCh 1CDh 1CEh 1CFh 1D0h 1D1h 1D2h 1D3h 1D4h 1D5h 1D6h 1D7h 1D8h-1FFh NAME THF -- TDS0M -- TBCS1 TBCS2 TBCS3 TBCS4 TCBR1 TCBR2 TCBR3 TCBR4 THSCS1 THSCS2 THSCS3 THSCS4 TGCCS1 TGCCS2 TGCCS3 TGCCS4 PCL1 PCL2 PCL3 PCL4 TBPCS1 TBPCS2 TBPCS3 TBPCS4 -- DESCRIPTION Transmit HDLC FIFO Register Reserved Transmit DS0 Monitor Register Reserved Transmit Blank Channel Select Register 1 Transmit Blank Channel Select Register 2 Transmit Blank Channel Select Register 3 Transmit Blank Channel Select Register 4 (E1 Mode Only) Transmit Channel Blocking Register 1 Transmit Channel Blocking Register 2 Transmit Channel Blocking Register 3 Transmit Channel Blocking Register 4 (E1 Mode Only) Transmit Hardware-Signaling Channel Select Register 1 Transmit Hardware-Signaling Channel Select Register 2 Transmit Hardware-Signaling Channel Select Register 3 Transmit Hardware-Signaling Channel Select Register 4 (E1 Mode Only) Transmit Gapped-Clock Channel Select Register 1 Transmit Gapped-Clock Channel Select Register 2 Transmit Gapped-Clock Channel Select Register 3 Transmit Gapped-Clock Channel Select Register 4 (E1 Mode Only) Per-Channel Loopback Enable Register 1 Per-Channel Loopback Enable Register 2 Per-Channel Loopback Enable Register 3 Per-Channel Loopback Enable Register 4 (E1 Mode Only) Transmit BERT Port Channel Select Register 1 Transmit BERT Port Channel Select Register 2 Transmit BERT Port Channel Select Register 3 Transmit BERT Port Channel Select Register 4 (E1 Mode Only) Reserved R/W W -- R -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- 105 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.1.3 LIU and BERT Register List Table 10-4. LIU Register List Note that only the LIU 1 address is presented here. The same set of registers definitions applies for LIUs 2 to 8 in accordance with the DS26518 map offsets. LIU offset is [1000+ (n - 1) x 20 hex], where n designates the LIU in question. LIU REGISTER LIST ADDRESS 1000h 1001h 1002h 1003h 1004h 1005h 1006h 1007 1008h 1009h-101Fh NAME LTRCR LTIPSR LMCR LRSR LSIMR LLSR LRSL LRISMR LRCR -- DESCRIPTION LIU Transmit Receive Control Register LIU Transmit Impedance and Pulse Shape Selection Register LIU Maintenance Control Register LIU Real Status Register LIU Status Interrupt Mask Register LIU Latched Status Register LIU Receive Signal Level Register LIU Receive Impedance and Sensitivity Monitor Register LIU Receive Control Register Reserved Table 10-5. BERT Register List Note that only the BERT 1 address is presented here. The same set of registers definitions applies for BERTs 2 to 8 in accordance with the DS26518 map offsets. BERT offset is [1100+ (n - 1) x 10 hex], where n designates the BERT channel in question. BERT REGISTER LIST ADDRESS 1100h 1101h 1102h 1103h 1104h 1105h 1106h 1107h 1108h 1109h 110Ah 110Bh 110Ch 110Dh 110Eh 110Fh NAME BAWC BRP1 BRP2 BRP3 BRP4 BC1 BC2 BBC1 BBC2 BBC3 BBC4 BEC1 BEC2 BEC3 BLSR BSIM DESCRIPTION BERT Alternating Word Count Rate Register BERT Repetitive Pattern Set Register 1 BERT Repetitive Pattern Set Register 2 BERT Repetitive Pattern Set Register 3 BERT Repetitive Pattern Set Register 4 BERT Control Register 1 BERT Control Register 2 BERT Bit Count Register 1 BERT Bit Count Register 2 BERT Bit Count Register 3 BERT Bit Count Register 4 BERT Error Count Register 1 BERT Error Count Register 2 BERT Error Count Register 3 BERT Latched Status Register BERT Status Interrupt Mask Register 106 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.2 Register Bit Maps 10.2.1 Global Register Bit Map Table 10-6. Global Register Bit Map ADDR 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh NAME GTCR1 GFCR1 GTCR3 GTCCR1 GTCCR3 -- GSRR1 -- IDR GFISR1 GBISR1 GLISR1 GFIMR1 GBIMR1 GLIMR1 BIT 7 GPSEL3 IBOMS1 -- BPREFSEL3 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GPSEL2 GPSEL1 -- 528MD GIBO GCLE GIPI IBOMS0 BPCLK1 BPCLK0 -- RFMSS TCBCS RCBCS TSSYNCIOSEL TSYNCSEL -- -- -- -- -- BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL FREQSEL MPS1 MPS0 RSYSCLKSEL TSYSCLKSEL TCLKSEL CLKOSEL3 CLKOSEL2 CLKOSEL1 CLKOSEL0 -- -- -- -- -- -- -- -- -- -- -- LRST BRST FRST -- -- -- -- -- -- -- ID6 ID5 ID4 ID3 ID2 ID1 ID0 FIS7 FIS6 FIS5 FIS4 FIS3 FIS2 FIS1 BIS7 BIS6 BIS5 BIS4 BIS3 BIS2 BIS1 LIS7 LIS6 LIS5 LIS4 LIS3 LIS2 LIS1 FIM7 FIM6 FIM5 FIM4 FIM3 FIM2 FIM1 BIM7 BIM6 BIM5 BIM4 BIM3 BIM2 BIM1 LIM7 LIM6 LIM5 LIM4 LIM3 LIM2 LIM1 -- -- -- ID7 FIS8 BIS8 LIS8 FIM8 BIM8 LIM8 107 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.2.2 Framer Register Bit Map Table 10-7 contains the framer registers of the DS26518. Some registers have dual functionality based on the selection of T1/J1 or E1 operating mode in the RMMR and TMMR registers. These dual-function registers are shown below using two lines of text. The first line of text is the bit functionality for T1/J1 mode. The second line is the bit functionality in E1 mode, in italics. Bits that are not used for an operating mode are denoted with a single dash "--". When there is only one set of bit definitions listed for a register, the bit functionality does not change with respect to the selection of T1/J1 or E1 mode. All registers not listed are reserved and should be initialized with a value of 00h for proper operation. The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following formula: Address for Framer n = (Framer 1 address + (n - 1) x 200hex). Table 10-7. Framer Register Bit Map ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 000h 001h 002h 003h 010h 011h 012h 013h 014h 015h 020h 021h 022h 023h 024h 025h 026h 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 02Fh 030h 031h 032h 033h 034h 035h 036h 037h 038h 039h E1RDMWE1 E1RDMWE2 E1RDMWE3 E1RDMWE4 RHC RHBSE RDS0SEL RSIGC T1RCR2 E1RSAIMR T1RBOCC RIDR1 RIDR2 RIDR3 RIDR4 RIDR5 RIDR6 RIDR7 RIDR8 RIDR9 RIDR10 RIDR11 RIDR12 RIDR13 RIDR14 RIDR15 RIDR16 RIDR17 RIDR18 RIDR19 RIDR20 RIDR21 RIDR22 RIDR23 RIDR24 T1RSAOI1 RIDR25 T1RSAOI2 RIDR26 CH8 CH16 CH24 CH32 RCRCD BSE8 -- -- -- -- -- CH7 CH15 CH23 CH31 RHR BSE7 -- -- -- -- -- CH6 CH14 CH22 CH30 RHMS BSE6 -- -- -- -- -- CH5 CH13 CH21 CH29 RHCS4 BSE5 RCM4 RFSA1 CASMS RSLC96 RSa4IM CH4 CH12 CH20 CH28 RHCS3 BSE4 RCM3 -- -- OOF2 RSa5IM CH3 CH11 CH19 CH27 RHCS2 BSE3 RCM2 RSFF RSFF OOF1 RSa6IM CH2 CH10 CH18 CH26 RHCS1 BSE2 RCM1 RSFE RSFE RAIIE RSa7IM CH1 CH9 CH17 CH25 RHCS0 BSE1 RCM0 RSIE RSEI RRAIS RSa8IM RBR C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 CH8 C7 CH16 C7 -- C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 CH7 C6 CH15 C6 RBD1 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 CH6 C5 CH14 C5 RBD0 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 CH5 C4 CH13 C4 -- C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 CH4 C3 CH12 C3 RBF1 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 CH3 C2 CH11 C2 RBF0 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 CH2 C1 CH10 C1 -- C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 CH1 C0 CH9 C0 108 of 286 DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 03Ah 03Bh 03Ch 03Dh 03Eh 03Fh 040h 041h 042h 043h 044h 045h 046h 047h 048h 049h 04Ah 04Bh 04Ch 04Dh 04Eh 04Fh 050h 051h 052h 053h T1RSAOI3 RIDR27 RIDR28 CH24 C7 -- C7 CH23 C6 -- C6 CH22 C5 -- C5 CH21 C4 -- C4 CH20 C3 -- C3 CH19 C2 -- C2 CH18 C1 -- C1 CH17 C0 -- C0 T1RDMWE1 RIDR29 T1RDMWE2 RIDR30 T1RDMWE3 RIDR31 RIDR32 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 CH8 C7 CH16 C7 CH24 C7 -- C7 CH1-A 0 CH2-A CH1-A CH7 C6 CH15 C6 CH23 C6 -- C6 CH1-B 0 CH2-B CH1-B CH6 C5 CH14 C5 CH22 C5 -- C5 CH1-C 0 CH2-C CH1-C CH5 C4 CH13 C4 CH21 C4 -- C4 CH1-D 0 CH2-D CH1-D CH4 C3 CH12 C3 CH20 C3 -- C3 CH13-A X CH14-A CH16-A CH3 C2 CH11 C2 CH19 C2 -- C2 CH13-B Y CH14-B CH16-B CH2 C1 CH10 C1 CH18 C1 -- C1 CH13-C X CH14-C CH16-C CH1 C0 CH9 C0 CH17 C0 -- C0 CH13-D X CH14-D CH16-D CH3-A CH2-A CH3-B CH2-B CH3-C CH2-C CH3-D CH2-D CH15-A CH17-A CH15-B CH17-B CH15-C CH17-C CH15-D CH17-D CH4-A CH3-A CH4-B CH3-B CH4-C CH3-C CH4-D CH3-D CH16-A CH18-A CH16-B CH18-B CH16-C CH18-C CH16-D CH18-D CH5-A CH4-A CH5-B CH4-B CH5-C CH4-C CH5-D CH4-D CH17-A CH19-A CH17-B CH19-B CH17-C CH19-C CH17-D CH19-D CH6-A CH5-A CH7-A CH6-A CH8-A CH7-A CH9-A CH8-A CH10-A CH9-A CH11-A CH10-A CH12-A CH11-A CH6-B CH5-B CH7-B CH6-B CH8-B CH7-B CH9-B CH8-B CH10-B CH9-B CH11-B CH10-B CH12-B CH11-B CH6-C CH5-C CH7-C CH6-C CH8-C CH7-C CH9-C CH8-C CH10-C CH9-C CH11-C CH10-C CH12-C CH11-C CH6-D CH5-D CH7-D CH6-D CH8-D CH7-D CH9-D CH8-D CH10-D CH9-D CH11-D CH10-D CH12-D CH11-D CH18-A CH20-A CH19-A CH21-A CH20-A CH22-A CH21-A CH23-A CH22-A CH24-A CH23-A CH25-A CH24-A CH26-A CH18-B CH20-B CH19-B CH21-B CH20-B CH22-B CH21-B CH23-B CH22-B CH24-B CH23-B CH25-B CH24-B CH26-B CH18-C CH20-C CH19-C CH21-C CH20-C CH22-C CH21-C CH23-C CH22-C CH24-C CH23-C CH25-C CH24-C CH26-C CH18-D CH20-D CH19-D CH21-D CH20-D CH22-D CH21-D CH23-D CH22-D CH24-D CH23-D CH25-D CH24-D CH26-D -- CH12-A -- CH13-A -- CH14-A -- CH15-A LCVC15 LCVC7 PCVC15 PCVC7 -- CH12-B -- CH13-B -- CH14-B -- CH15-B LCVC14 LCVC6 PCVC14 PCVC6 -- CH12-C -- CH13-C -- CH14-C -- CH15-C LCVC13 LCVC5 PCVC13 PCVC5 -- CH12-D -- CH13-D -- CH14-D -- CH15-D LCVC12 LCVC4 PCVC12 PCVC4 -- CH27-A -- CH28-A -- CH29-A -- CH30-A LCVC11 LCVC3 PCVC11 PCVC3 -- CH27-B -- CH28-B -- CH29-B -- CH30-B LCVC10 LCVC2 PCVC10 PCVC2 -- CH27-C -- CH28-C -- CH29-C -- CH30-C LCVC9 LCVC1 PCVC9 PCVC1 -- CH27-D -- CH28-D -- CH29-D -- CH30-D LCVC8 LCVC0 PCVC8 PCVC0 LCVCR1 LCVCR2 PCVCR1 PCVCR2 109 of 286 DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 054h 055h 056h 057h 058h 059h 05Ah 05Bh 060h 061h 062h 063h 064h 065h 066h 067h 068h 069h 06Ah 06Bh 06Ch 06Dh 06Eh 06Fh 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 090h 091h 092h FOSCR1 FOSCR2 E1EBCR1 E1EBCR2 FEACR1 FEACR2 FEBCR1 FEBCR2 RDS0M -- T1RFDL E1RRTS7 FOS15 FOS7 EB15 EB7 FEACR15 FEACR7 FEBCR15 FEBCR7 B1 -- RFDL7 CSC5 FOS14 FOS6 EB14 EB6 FEACR14 FEACR6 FEBCR14 FEBCR6 B2 -- RFDL6 CSC4 FOS13 FOS5 EB13 EB5 FEACR13 FEACR5 FEBCR13 FEBCR5 B3 -- RFDL5 CSC3 FOS12 FOS4 EB12 EB4 FEACR12 FEACR4 FEBCR12 FEBCR4 B4 -- RFDL4 CSC2 FOS11 FOS3 EB11 EB3 FEACR11 FEACR3 FEBCR11 FEBCR3 B5 -- RFDL3 CSC0 FOS10 FOS2 EB10 EB2 FEACR10 FEACR2 FEBCR10 FEBCR2 B6 -- RFDL2 CRC4SA FOS9 FOS1 EB9 EB1 FEACR9 FEACR1 FEBCR9 FEBCR1 B7 -- RFDL1 CASSA FOS8 FOS0 EB8 EB0 FEACR8 FEACR0 FEBCR8 FEBCR0 B8 -- RFDL0 FASSA T1RBOC T1RSLC1 E1RAF T1RSLC2 E1RNAF T1RSLC3 E1RsiAF E1RSiNAF E1RRA E1RSa4 E1RSa5 E1RSa6 E1RSa7 E1RSa8 SaBITS Sa6CODE RMMR RCR1 (T1) RCR1 (E1) T1RIBCC E1RCR2 RCR3 RIOCR RESCR ERCNT RHFC RIBOC T1RSCC RXPC RBPBS RLS1 RLS2 (T1) RLS2 (E1) -- C8 Si M2 Si S=1 SiF14 SiF15 RRAF15 RSa4F15 RSa5F15 RSa6F15 RSa7F15 RSa8F15 -- -- FRM_EN SYNCT -- -- -- -- RCLKINV RCLKINV -- C7 0 M1 1 S4 SiF12 SiF13 RRAF13 RSa4F13 RSa5F13 RSa6F13 RSa7F13 RSa8F13 -- -- INIT_DONE RB8ZS RHDB3 -- -- uALAW RSYNCINV RSYNCINV RBOC5 C6 0 S=0 A S3 SiF10 SiF11 RRAF11 RSa4F11 RSa5F11 RSa6F11 RSa7F11 RSa8F11 -- -- -- RFM RSIGM RUP2 -- RSERC H100EN H100EN RBOC4 C5 1 S=1 Sa4 S2 SiF8 SiF9 RRAF9 RSa4F9 RSa5F9 RSa6F9 RSa7F9 RSa8F9 Sa4 -- -- ARC RG802 RUP1 -- BINV1 RSCLKM RSCLKM RBOC3 C4 1 S=0 Sa5 S1 SiF6 SiF7 RRAF7 RSa4F7 RSa5F7 RSa6F7 RSa7F7 RSa8F7 Sa5 Sa6n -- SYNCC RCRC4 RUP0 -- BINV0 RSMS -- RESALGN EAMS EAMS -- IBOEN -- -- -- BPBSE4 RRAID 16ZD RSA1 RBOC2 C3 0 C11 Sa6 A2 SiF4 SiF5 RRAF5 RSa4F5 RSa5F5 RSa6F5 RSa7F5 RSa8F5 Sa6 Sa6n -- RJC FRC RDN2 -- -- RSIO RSIO RBOC1 C2 1 C10 Sa7 A1 SiF2 SiF3 RRAF3 RSa4F3 RSa5F3 RSa6F3 RSa7F3 RSa8F3 Sa7 Sa6n SFTRST SYNCE SYNCE RDN1 -- PLB RSMS2 RSMS2 RBOC0 C1 1 C9 Sa8 M3 SiF0 SiF1 RRAF1 RSa4F1 RSa5F1 RSa6F1 RSa7F1 RSa8F1 Sa8 Sa6n T1/E1 RESYNC RESYNC RDN0 RLOSA FLB RSMS1 RSMS1 RDATFMT 1SECS 1SECS -- -- -- -- -- BPBSE8 RRAIC -- -- RGCLKEN MCUS MCUS -- -- -- -- -- BPBSE7 RAISC -- CRCRC -- MECU MECU -- -- -- -- -- BPBSE6 RLOSC COFA CASRC RSZS ECUS ECUS -- IBOSEL -- -- -- BPBSE5 RLOFC 8ZD FASRC RESR FSBE -- -- -- RSC2 RBPDIR RBPDIR RESMDM MOSCRF -- RFHWM1 -- RSC1 RBPFUS -- BPBSE2 RLOSD B8ZS RCMF RESE LCVCRF LCVCRF RFHWM0 -- RSC0 RBPEN RBPEN BPBSE3 RAISD SEFE RSA0 BPBSE1 RLOFD FBE RAF RLS3 (T1) LORCC LSPC LDNC LUPC LORCD LSPD LDND LUPD 110 of 286 DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME RLS3 (E1) BIT 7 LORCC BIT 6 BIT 5 V52LNKC BIT 4 RDMAC BIT 3 LORCD BIT 2 BIT 1 V52LNKD BIT 0 RDMAD -- RESEM -- -- -- -- CH7 CH15 CH23 -- CH31 C6 -- C6 -- RLS7 RAISC -- -- LSPC -- RESEM -- -- -- 1SEC RPS RFDLF -- -- CH3 CH11 CH19 -- CH27 C2 -- C2 -- RLS3 RAISD -- RSA0 LSPD -- 1SEC RPS RFDLF -- CH3 CH11 CH19 093h 094h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Fh 0A0h 0A1h 0A2h 0A3h 0A4h 0A6h 0A8h 0A9h 0AAh 0ABh 0ACh 0ADh 0AEh 0AFh 0B0h 0B2h 0B4h 0B5h 0B6h 0C0h 0C1h 0C2h 0C3h 0C4h RLS4 RLS5 RLS7 (T1) RLS7 (E1) -- RSS1 RSS2 RSS3 RESF -- -- -- -- CH8 CH16 CH24 -- CH32 C7 -- C7 -- -- RRAIC -- -- LORCC LORCC RESF -- -- RSLIP ROVR RRAI-CI -- -- CH6 CH14 CH22 -- CH30 C5 -- C5 -- RLS6* RLOSC -- -- LDNC V52LNKC RSLIP ROVR RRAI-CI -- CH6 CH14 CH22 -- RHOBT RAIS-CI -- -- CH5 CH13 CH21 -- CH29 C4 -- C4 -- RLS5 RLOFC -- -- LUPC RDMAC -- RHOBT RAIS-CI -- CH5 CH13 CH21 RSCOS RPE RSLC96 -- -- CH4 CH12 CH20 -- CH28 C3 -- C3 -- RLS4 RRAID -- RSA1 LORCD LORCD RSCOS RPE RSLC96 -- CH4 CH12 CH20 TIMER RHWMS BC Sa6CD -- CH2 CH10 CH18 -- CH26 C1 -- C1 -- RLS2** RLOSD -- RCMF LDND V52LNKD TIMER RHWMS BC Sa6CD CH2 CH10 CH18 RMF RNES BD SaXCD -- CH1 CH9 CH17 -- CH25 C0 -- C0 -- RLS1 RLOFD -- RAF LUPD RDMAD RMF RNES BD SaXCD CH1 CH9 CH17 RSS4 T1RSCD1 T1RSCD2 RIIR RIM1 RIM2 RIM3 (T1) RIM3 (E1) RIM4 RIM5 RIM7 (T1) RIM7 (E1) RSCSE1 RSCSE2 RSCSE3 RSCSE4 CH8 CH16 CH24 CH7 CH15 CH23 -- CH32 C7 -- C7 -- C7 -- C7 -- -- -- -- -- MS RHD7 CH8 CH16 CH24 -- CH32 CH8 -- CH31 C6 -- C6 -- C6 -- C6 -- -- -- -- PS2 RPBA6 RHD6 CH7 CH15 CH23 -- CH31 CH7 -- CH30 C5 -- C5 -- C5 -- C5 -- -- -- -- PS1 RPBA5 RHD5 CH6 CH14 CH22 -- CH30 CH6 -- CH29 C4 -- C4 -- C4 -- C4 -- -- -- -- PS0 RPBA4 RHD4 CH5 CH13 CH21 -- CH29 CH5 -- CH28 C3 -- C3 -- C3 -- C3 -- RRAI LORC LORC -- RPBA3 RHD3 CH4 CH12 CH20 -- CH28 CH4 -- CH27 C2 -- C2 -- C2 -- C2 -- RAIS LSP -- -- RPBA2 RHD2 CH3 CH11 CH19 -- CH27 CH3 -- CH26 C1 -- C1 -- C1 -- C1 -- RLOS LDN V52LNK RHWM RPBA1 RHD1 CH2 CH10 CH18 -- CH26 CH2 -- CH25 C0 -- C0 -- C0 -- C0 -- RLOF LUP RDMA RNE RPBA0 RHD0 CH1 CH9 CH17 -- CH25 CH1 T1RUPCD1 T1RUPCD2 T1RDNCD1 T1RDNCD2 RRTS1 RRTS3 (T1) RRTS3 (E1) RRTS5 RHPBA RHF RBCS1 RBCS2 RBCS3 RBCS4 RCBR1 111 of 286 DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0C5h 0C6h 0C7h 0C8h 0C9h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 110h 111h 113h 118h 119h 11Ah 11Bh 120h 121h 122h 123h 124h 125h RCBR2 RCBR3 RCBR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 RCICE4 CH16 CH24 -- CH32 CH8 CH16 CH24 -- CH32 CH8 CH16 CH24 -- CH32 CH8 CH16 CH24 -- CH32 CH15 CH23 -- CH31 CH7 CH15 CH23 -- CH31 CH7 CH15 CH23 -- CH31 CH7 CH15 CH23 -- CH31 CH14 CH22 -- CH30 CH6 CH14 CH22 -- CH30 CH6 CH14 CH22 -- CH30 CH6 CH14 CH22 -- CH30 CH13 CH21 -- CH29 CH5 CH13 CH21 -- CH29 CH5 CH13 CH21 -- CH29 CH5 CH13 CH21 -- CH29 CH12 CH20 -- CH28 CH4 CH12 CH200 -- CH28 CH4 CH12 CH20 -- CH28 CH4 CH12 CH20 -- CH28 CH11 CH19 -- CH27 CH3 CH11 CH19 -- CH27 CH3 CH11 CH19 -- CH27 CH3 CH11 CH19 -- CH27 CH10 CH18 -- CH26 CH2 CH10 CH18 -- CH26 CH2 CH10 CH18 -- CH26 CH2 CH10 CH18 -- CH26 CH9 CH17 -- CH25(F-bit) CH1 CH9 CH17 -- CH25 CH1 CH9 CH17 -- CH25(F-bit) CH1 CH9 CH17 -- CH25 RBPCS1 RBPCS2 RBPCS3 RBPCS4 CH8 CH16 CH24 -- CH32 CH7 CH15 CH23 -- CH31 CH6 CH14 CH22 -- CH30 CH5 CH13 CH21 -- CH29 CH4 CH12 CH20 -- CH28 CH3 CH11 CH19 -- CH27 CH2 CH10 CH18 -- CH26 CH1 CH9 CH17 -- CH25 TDMWE1 TDMWE2 TDMWE3 TDMWE4 TJBE1 TJBE2 TJBE3 TJBE4 TDDS1 TDDS2 TDDS3 THC1 THBSE THC2 SSIE1 SSIE2 SSIE3 SSIE4 CH8 CH16 CH24 CH32 CH8 CH16 CH24 CH32 CH8 CH16 CH24 NOFS TBSE8 TABT TABT CH7 CH15 CH23 CH31 CH7 CH15 CH23 CH31 CH7 CH15 CH23 TEOML TBSE7 SBOC -- CH6 CH14 CH22 CH30 CH6 CH14 CH22 CH30 CH6 CH14 CH22 THR TBSE6 THCEN THCEN CH5 CH13 CH21 CH29 CH5 CH13 CH21 CH29 CH5 CH13 CH21 THMS TBSE5 THCS4 THCS4 CH4 CH12 CH20 CH28 CH4 CH12 CH20 CH28 CH4 CH12 CH20 TFS TBSE4 THCS3 THCS3 CH3 CH11 CH19 CH27 CH3 CH11 CH19 CH27 CH3 CH11 CH19 TEOM TBSE3 THCS2 THCS2 CH2 CH10 CH18 CH26 CH2 CH10 CH18 CH26 CH2 CH10 CH18 TZSD TBSE2 THCS1 THCS1 CH1 CH9 CH17 CH25 CH1 CH9 CH17 CH25 CH1 CH9 CH17 TCRCD TBSE1 THCS0 THCS0 CH8 CH16 CH24 -- CH32 C7 C7 C7 C7 C7 C7 CH7 CH15 CH23 -- CH31 C6 C6 C6 C6 C6 C6 CH6 CH14 CH22 -- CH30 C5 C5 C5 C5 C5 C5 CH5 CH13 CH21 -- CH29 C4 C4 C4 C4 C4 C4 CH4 CH12 CH20 -- CH28 C3 C3 C3 C3 C3 C3 CH3 CH11 CH19 -- CH27 C2 C2 C2 C2 C2 C2 CH2 CH10 CH18 -- CH26 C1 C1 C1 C1 C1 C1 CH1 CH9 CH17 -- CH25 C0 C0 C0 C0 C0 C0 TIDR1 TIDR2 TIDR3 TIDR4 TIDR5 TIDR6 112 of 286 DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 126h 127h 128h 129h 12Ah 12Bh 12Ch 12Dh 12Eh 12Fh 130h 131h 132h 133h 134h 135h 136h 137h 138h 139h 13Ah 13Bh 13Ch 13Dh 13Eh 13Fh 140h 141h 142h 143h 144h 145h 146h 147h TIDR7 TIDR8 TIDR9 TIDR10 TIDR11 TIDR12 TIDR13 TIDR14 TIDR15 TIDR16 TIDR17 TIDR18 TIDR19 TIDR20 TIDR21 TIDR22 TIDR23 TIDR24 TIDR25 TIDR26 TIDR27 TIDR28 TIDR29 TIDR30 TIDR31 TIDR32 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 -- C7 -- C7 -- C7 -- C7 -- C7 -- C7 -- C7 -- C7 CH1-A 0 CH2-A CH1-A CH3-A CH2-A CH4-A CH3-A CH5-A CH4-A CH6-A CH5-A CH7-A CH6-A CH8-A C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 -- C6 -- C6 -- C6 -- C6 -- C6 -- C6 -- C6 -- C6 CH1-B 0 CH2-B CH1-B CH3-B CH2-B CH4-B CH3-B CH5-B CH4-B CH6-B CH5-B CH7-B CH6-B CH8-B C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 -- C5 -- C5 -- C5 -- C5 -- C5 -- C5 -- C5 -- C5 CH1-C 0 CH2-C CH1-C CH3-C CH2-C CH4-C CH3-C CH5-C CH4-C CH6-C CH5-C CH7-C CH6-C CH8-C C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 -- C4 -- C4 -- C4 -- C4 -- C4 -- C4 -- C4 -- C4 CH1-D 0 CH2-D CH1-D CH3-D CH2-D CH4-D CH3-D CH5-D CH4-D CH6-D CH5-D CH7-D CH6-D CH8-D C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 -- C3 -- C3 -- C3 -- C3 -- C3 -- C3 -- C3 -- C3 CH13-A X CH14-A CH16-A CH15-A CH17-A CH16-A CH18-A CH17-A CH19-A CH18-A CH20-A CH19-A CH21-A CH20-A C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 -- C2 -- C2 -- C2 -- C2 -- C2 -- C2 -- C2 -- C2 CH13-B Y CH14-B CH16-B CH15-B CH17-B CH16-B CH18-B CH17-B CH19-B CH18-B CH20-B CH19-B CH21-B CH20-B C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 -- C1 -- C1 -- C1 -- C1 -- C1 -- C1 -- C1 -- C1 CH13-C X CH14-C CH16-C CH15-C CH17-C CH16-C CH18-C CH17-C CH19-C CH18-C CH20-C CH19-C CH21-C CH20-C C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 -- C0 -- C0 -- C0 -- C0 -- C0 -- C0 -- C0 -- C0 CH13-D X CH14-D CH16-D CH15-D CH17-D CH16-D CH18-D CH17-D CH19-D CH18-D CH20-D CH19-D CH21-D CH20-D TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 113 of 286 DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 CH7-A CH9-A CH8-A CH10-A CH9-A CH11-A CH10-A CH12-A CH11-A -- CH12-A -- CH13-A -- CH14-A -- CH15-A CH8 CH16 CH24 -- CH32 TFDL7 -- -- -- C8 Si M2 Si S=1 TSiF14 -- TsiF15 -- TRAF15 -- TSa4F15 -- TSa5F15 -- TSa6F15 -- TSa7F15 -- TSa8F15 FRM_EN TJC TTPT BIT 6 CH7-B CH9-B CH8-B CH10-B CH9-B CH11-B CH10-B CH12-B CH11-B -- CH12-B -- CH13-B -- CH14-B -- CH15-B CH7 CH15 CH23 -- CH31 TFDL6 -- -- -- C7 0 M1 1 S4 TSiF12 -- TSiF13 -- TRAF13 -- TSa4F13 -- TSa5F13 -- TSa6F13 -- TSa7F13 -- TSa8F13 INIT_DONE BIT 5 CH7-C CH9-C CH8-C CH10-C CH9-C CH11-C CH10-C CH12-C CH11-C -- CH12-C -- CH13-C -- CH14-C -- CH15-C CH6 CH14 CH22 -- CH30 TFDL5 -- TBOC5 -- C6 0 S=0 A S3 TSiF10 -- TSiF11 -- TRAF11 -- TSa4F11 -- TSa5F11 -- TSa6F11 -- TSa7F11 -- TSa8F11 -- TCPT TG802 BIT 4 CH7-D CH9-D CH8-D CH10-D CH9-D CH11-D CH10-D CH12-D CH11-D -- CH12-D -- CH13-D -- CH14-D -- CH15-D CH5 CH13 CH21 -- CH29 TFDL4 -- TBOC4 -- C5 1 S=1 Sa4 S2 TSiF8 -- TSiF9 -- TRAF9 -- TSa4F9 -- TSa5F9 -- TSa6F9 -- TSa7F9 -- TSa8F9 -- TSSE TSiS BIT 3 CH22-A CH21-A CH23-A CH22-A CH24-A CH23-A CH25-A CH24-A CH26-A -- CH27-A -- CH28-A -- CH29-A -- CH30-A CH4 CH12 CH20 -- CH28 TFDL3 -- TBOC3 -- C4 1 S=0 Sa5 S1 TSiF6 -- TSiF7 -- TRAF7 -- TSa4F7 -- TSa5F7 -- TSa6F7 -- TSa7F7 -- TSa8F7 -- GB7S TSA1 BIT 2 CH22-B CH21-B CH23-B CH22-B CH24-B CH23-B CH25-B CH24-B CH26-B -- CH27-B -- CH28-B -- CH29-B -- CH30-B CH3 CH11 CH19 -- CH27 TFDL2 -- TBOC2 -- C3 0 C11 Sa6 A2 TSiF4 -- TSiF5 -- TRAF5 -- TSa4F5 -- TSa5F5 -- TSa6F5 -- TSa7F5 -- TSa8F5 -- TB8ZS THDB3 BIT 1 CH22-C CH21-C CH23-C CH22-C CH24-C CH23-C CH25-C CH24-C CH26-C -- CH27-C -- CH28-C -- CH29-C -- CH30-C CH2 CH10 CH18 -- CH26 TFDL1 -- TBOC1 -- C2 1 C10 Sa7 A1 TSiF2 -- TSiF3 -- TRAF3 -- TSa4F3 -- TSa5F3 -- TSa6F3 -- TSa7F3 -- TSa8F3 SFTRST TAIS TAIS BIT 0 CH22-D CH21-D CH23-D CH22-D CH24-D CH23-D CH25-D CH24-D CH26-D -- CH27-D -- CH28-D -- CH29-D -- CH30-D CH1 CH9 CH17 -- CH25 TFDL0 -- TBOC0 -- C1 1 C9 Sa8 M3 TSiF0 -- TSiF1 -- TRAF1 -- TSa4F1 -- TSa5F1 -- TSa6F1 -- TSa7F1 -- TSa8F1 T1/E1 TRAI TCRC4 148h 149h 14Ah 14Bh 14Ch 14Dh 14Eh 14Fh 150h 151h 152h 153h 162h 163h 164h 165h 166h 167h 168h 169h 16Ah 16Bh 16Ch 16Dh 180h 181h TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 TCICE1 TCICE2 TCICE3 TCICE4 T1TFDL T1TBOC T1TSLC1 E1TAF T1TSLC2 E1TNAF T1TSLC3 E1TSiAF E1TSiNAF E1TRA E1TSa4 E1TSa5 E1TSa6 E1TSa7 E1TSa8 TMMR TCR1 (T1) TCR1 (E1) TFPT T16S 114 of 286 DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 182h T1.TCR2 (T1) E1.TCR2 (E1) TCR3 TIOCR TESCR TCR4 THFC TIBOC TDS0SEL TXPC TBPBS TSYNCC TLS1 TLS2 TLS3 TIIR TIM1 TIM2 TIM3 T1TCD1 T1TCD2 TRTS2 TFBA THF TDS0M TBCS1 TBCS2 TBCS3 TBCS4 TFDLS AEBE TSLC96 AAIS TDDSEN ARA FBCT2 -- FBCT1 -- TRAIS -- -- -- TB7ZS -- 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Eh 190h 191h 192h 19Fh 1A0h 1A1h 1A2h 1ACh ADh 1B1h 1B3h 1B4h 1BBh 1C0h 1C1h 1C2h 1C3h 1C4h 1C5h 1C6h 1C7h 1C8h 1C9h -- -- -- -- TSYNCINV TSYNCINV TCSS1 TCSS1 TSSYNCINV TSSYNCINV TCSS0 TCSS0 MFRS MFRS TFM -- IBPV IBPV TLOOP CRC4R TCLKINV TCLKINV TSCLKM TSCLKM TSSM TSSM TSIO TSIO TSDW -- TSM TSM TDATFMT uALAW uALAW TGCLKEN BINV1 BINV1 ---- BINV0 BINV0 TSZS TJBEN TJBEN TESALGN TRAIM -- TESR TAISM -- TESMDM TC1 -- TESE TC0 -- -- -- -- -- BPBSE8 -- -- -- -- -- -- BPBSE7 -- -- -- -- -- -- BPBSE6 -- -- -- IBOSEL TCM4 -- BPBSE5 -- -- -- IBOEN TCM3 -- BPBSE4 -- CRC4 -- -- TCM2 TBPDIR BPBSE3 TSEN TSEN TFLWM1 -- TCM1 TBPFUS BPBSE2 SYNCE SYNCE TFLWM0 -- TCM0 TBPEN BPBSE1 RESYNC RESYNC TESF TESF TESEM TESEM TSLIP TSLIP TSLC96 -- -- TAF TMF TMF LOTCC LOTCC LOTC LOTC -- -- -- -- -- -- TFDLE -- TUDR TUDR TMEND TMEND TLWMS TLWMS TNFS TNFS -- -- TESF TESF -- -- TESEM TESEM -- -- TSLIP TSLIP -- -- TSLC96 -- -- -- -- TAF -- TLS3 TMF TMF LOF TLS2 LOTCC LOTCC LOFD TLS1 LOTC LOTC -- -- -- -- -- -- TFDLE -- TUDR TUDR TMEND TMEND TLWMS TLWMS TNFS TNFS -- C7 -- C7 -- -- ---- THD7 B1 CH8 CH16 CH24 -- CH32 CH8 CH16 CH24 -- CH32 CH8 CH16 -- C6 -- C6 -- -- TFBA6 THD6 B2 CH7 CH15 CH23 -- CH31 CH7 CH15 CH23 -- CH31 CH7 CH15 -- C5 -- C5 -- -- TFBA5 THD5 B3 CH6 CH14 CH22 -- CH30 CH6 CH14 CH22 -- CH30 CH6 CH14 -- C4 -- C4 -- -- TFBA4 THD4 B4 CH5 CH13 CH21 -- CH29 CH5 CH13 CH21 -- CH29 CH5 CH13 -- C3 -- C3 -- TEMPTY TFBA3 THD3 B5 CH4 CH12 CH20 -- CH28 CH4 CH12 CH20 -- CH28 CH4 CH12 -- C2 -- C2 -- TFULL TFBA2 THD2 B6 CH3 CH11 CH19 -- CH27 CH3 CH11 CH19 -- CH27 CH3 CH11 -- C1 -- C1 -- TLWM TFBA1 THD1 B7 CH2 CH10 CH18 -- CH26 CH2 CH10 CH18 -- CH26 CH2 CH10 LOFD C0 -- C0 -- TNF TFBA0 THD0 B8 CH1 CH9 CH17 -- CH25 CH1 CH9 CH17 -- CH25:Fbit CH1 CH9 TCBR1 TCBR2 TCBR3 TCBR4 THSCS1 THSCS2 115 of 286 DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1CAh 1CBh 1CCh 1CDh 1CEh 1CFh 1D0h 1D1h 1D2h 1D3h 1D4h 1D5h 1D6h 1D7h THSCS3 THSCS4 CH24 -- CH32 CH23 -- CH31 CH22 -- CH30 CH21 -- CH29 CH20 -- CH28 CH19 -- CH27 CH18 -- CH26 CH17 -- CH25 TGCCS1 TGCCS2 TGCCS3 TGCCS4 CH8 CH16 CH24 -- CH32 CH7 CH15 CH23 -- CH31 CH6 CH14 CH22 -- CH30 CH5 CH13 CH21 -- CH29 CH4 CH12 CH20 -- CH28 CH3 CH11 CH19 -- CH27 CH2 CH10 CH18 -- CH26 CH1 CH9 CH17 -- CH25(F-bit) PCL1 PCL2 PCL3 PCL4 CH8 CH16 CH24 -- CH32 CH7 CH15 CH23 -- CH31 CH6 CH14 CH22 -- CH30 CH5 CH13 CH21 -- CH29 CH4 CH12 CH20 -- CH28 CH3 CH11 CH19 -- CH27 CH2 CH10 CH18 -- CH26 CH1 CH9 CH17 -- CH25 TBPCS1 TBPCS2 TBPCS3 TBPCS4 CH8 CH16 CH24 -- CH32 CH7 CH15 CH23 -- CH31 CH6 CH14 CH22 -- CH30 CH5 CH13 CH21 -- CH29 CH4 CH12 CH20 -- CH28 CH3 CH11 CH19 -- CH27 CH2 CH10 CH18 -- CH26 CH1 CH9 CH17 -- CH25 *RLS6 is reserved for future use. **Currently, RLS2 does not create an interrupt, therefore this bit is not used in T1 mode. 116 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.2.3 LIU Register Bit Map Table 10-8. LIU Register Bit Map ADDR NAME 1000h LTRCR 1001h LTIPSR 1002h LMCR 1003h LRSR 1004h LSIMR 1005h LLSR 1006h LRSL 1007h LRISMR 1008h LRCR 1009h- Test 101Fh Registers BIT 7 -- TG703 TAIS -- JALTCIM JALTC RSL3 -- RG703 BIT 6 RHPM TIMPTON ATAIS -- OCCIM OCC RSL2 RIMPON -- BIT 5 JADS1 TIMPL1 LB2 OEQ SCCIM SCC RLS1 -- -- BIT 4 JADS0 TIMPL0 LB1 UEQ LOSCIM LOSC RLS0 -- -- BIT 3 JAPS1 -- LB0 RSCS JALTSIM JALTS -- -- RTR BIT 2 JAPS0 L2 TPDE TSCS OCDIM OCD -- RIMPM2 RMONEN BIT 1 T1J1E1S L1 RPDE OCS SCDIM SCD -- RIMPM1 RSMS1 BIT 0 LSC L0 TE LOSS LOSDIM LOSD -- RIMPM0 RSMS0 -- -- -- -- -- -- -- -- 117 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.2.4 BERT Register Bit Map Table 10-9. BERT Register Bit Map ADDR NAME 1100h 1101h 1102h 1103h 1104h 1105h 1106h 1107h 1108h 1109h 110Ah 110Bh 110Ch 110Dh 110Eh 110Fh BAWC BRP1 BRP2 BRP3 BRP4 BC1 BC2 BBC1 BBC2 BBC3 BBC4 BEC1 BEC2 BEC3 BLSR BSIM BIT 7 ACNT7 RPAT7 RPAT15 RPAT23 RPAT31 TC EIB2 BBC7 BBC15 BBC23 BBC31 EC7 EC15 EC23 -- -- BIT 6 ACNT6 RPAT6 RPAT14 RPAT22 RPAT30 TINV EIB1 BBC6 BBC14 BBC22 BBC30 EC6 EC14 EC22 BBED BBED BIT 5 ACNT5 RPAT5 RPAT13 RPAT21 RPAT29 RINV EIB0 BBC5 BBC13 BBC21 BBC29 EC5 EC13 EC21 BBCO BBCO BIT 4 ACNT4 RPAT4 RPAT12 RPAT20 RPAT28 PS2 SBE BBC4 BBC12 BBC20 BBC28 EC4 EC12 EC20 BECO BECO BIT 3 ACNT3 RPAT3 RPAT11 RPAT19 RPAT27 PS1 RPL3 BBC3 BBC11 BBC19 BBC27 EC3 EC11 EC19 BRA1 BRA1 BIT 2 ACNT2 RPAT2 RPAT10 RPAT18 RPAT26 PS0 RPL2 BBC2 BBC10 BBC18 BBC26 EC2 EC10 EC18 BRA0 BRA0 BIT 1 ACNT1 RPAT1 RPAT9 RPAT17 RPAT25 LC RPL1 BBC1 BBC9 BBC17 BBC25 EC1 EC9 EC17 BRLOS BRLOS BIT 0 ACNT0 RPAT0 RPAT8 RPAT16 RPAT24 RESYNC RPL0 BBC0 BBC8 BBC16 BBC24 EC0 EC8 EC16 BSYNC BSYNC 118 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.3 Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK1 configuration. The global registers bit descriptions are presented below. Table 10-10. Global Register Set ADDRESS 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh Note 1: Note 2: NAME GTCR1 GFCR1 GTCR3 GTCCR1 GTCCR3 -- GSRR1 -- IDR GFISR1 GBISR1 GLISR1 GFIMR1 GBIMR1 GLIMR1 DESCRIPTION Global Transceiver Control Register 1 Global Framer Control Register 1 Global Transceiver Control Register 3 Global Transceiver Clock Control Register 1 Global Transceiver Clock Control Register 3 Reserved Global LIU Software Reset Register 1 Reserved Device Identification Register Global Framer Interrupt Status Register 1 Global BERT Interrupt Status Register 1 Global LIU Interrupt Status Register 1 Global Framers Interrupt Mask Register 1 Global BERT Interrupt Mask Register 1 Global LIU Interrupt Mask Register 1 R/W R/W R/W R/W R/W R/W -- R/W -- R R R R RW RW RW Reserved registers should only be written with all zeros. The global registers are located in the framer address space. The corresponding address space for the other seven framers is "Reserved," and should be initialized with all zeros for proper operation. 119 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name Register Description: Register Address: GTCR1 Global Transceiver Control Register 1 00F0h 6 GPSEL2 0 5 GPSEL1 0 4 -- 0 3 528MD 0 2 GIBO 0 1 GCLE 0 0 GIPI 0 Bit # Name Default 7 GPSEL3 0 Bits 7 to 5: General-Purpose I/O Pins Select (GPSEL[3:1]) Table 10-11. Output Status Control GPSEL[3:1] 000 001 010 011 100 101 110 111 RLF/LTC[8:1] RLF LTC RLF LTC RLF LTC Reserved Reserved AL/RSIGF/FLOS[8:1] AL AL RSIGF RSIGF FLOS FLOS Reserved Reserved Bit 3: DS26528 Mode (528MD) 0 = Normal operation. 1 = Pin definitions switch to DS26528 pins to obtain pin compatibility with the DS26528. Normal Operation 528MD RSYSCLK[8:2] RLF/LTC[8:2] RSYSCLK1 RSYSCLK1 CLKO RLF/LTC1 TSYSCLK[8:2] AL/RSIGF/FLOS[8:2] TSYSCLK1 TSYSCLK1 SPI_SEL AL/RSIGF/FLOS1 TSYNC/TSSYNCIO[8:1] TSYNC[8:1] (Tie low--unused) TSSYNCIO Bit 2: Ganged IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or an external "wire-OR" operation. Normally this bit should be set = 0 and the internal mux used. 0 = Use internal IBO mux. 1 = Externally "wire-OR" TSERn and RSERn for IBO operation. Note: Setting GIBO disables the internal IBO mux. GFCR1 must be set to inform the framers of the IBO configuration. Bit 1: Global Counter Latch Enable (GCLE). A low-to-high transition on this bit will, when enabled, latch the framer performance monitor counters. Each framer can be independently enabled to accept this input. This bit must be cleared and set again to perform another counter latch. Bit 0: Global Interrupt Pin Inhibit (GIPI) 0 = Normal Operation. Interrupt pin (INTB) will toggle low on an unmasked interrupt condition. 1 = Interrupt Inhibit. Interrupt pin (INTB) is forced high (inactive) when this bit is set. 120 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Description: Register Address: GFCR1 Global Framer Control Register 1 00F1h 6 IBOMS0 0 5 BPCLK1 0 4 BPCLK0 0 3 -- 0 2 RFMSS 0 1 TCBCS 0 0 RCBCS 0 the bits bits bits Bit # Name Default 7 IBOMS1 0 Bits 7 and 6: Interleave Bus Operation Mode Select 1 and 0 (IBOMS[1:0]). These bits determine configuration of the IBO (interleaved bus) multiplexer and inform the framers of the IBO configuration. These should be used in conjunction with the Rx and Tx IBO control registers within each of the framer units. These control Channels 1 to 8. Additional information concerning the IBO multiplexer is given in Section 9.8.2. These must be set whether using the internal IBO mux or externally ganging the pins. IBOMS1 0 0 1 1 IBOMS0 0 1 0 1 IBO Mode IBO disabled. 2 devices on bus (4.096MHz). 4 devices on bus (8.192MHz). 8 devices on bus (16.384MHz). Bits 5 and 4: Backplane Clock Select 1 and 0 (BPCLK[1:0]). These bits determine the clock frequency output on the BPCLK1 pin. BPCLK1 0 0 1 1 BPCLK0 0 1 0 1 BPCLK1 Frequency 2.048MHz 4.096MHz 8.192MHz 16.384MHz Bit 2: Receive Frame/Multiframe Sync Select (RFMSS). This bit controls the function of all eight RMSYNCn/RFSYNCn pins. 0 = RMSYNC/RFSYNC[8:1] pins output RFSYNC[8:1] (Receive Frame Sync) 1 = RMSYNC/RFSYNC[8:1] pins output RMSYNC[8:1] (Receive Multiframe Sync) Bit 1: Transmit Channel Block/Clock Select (TCBCS). This bit controls the function of all eight TCHBLKn/TCHCLKn pins. 0 = TCHBLK/TCHCLK[8:1] pins output TCHBLK[8:1] (Transmit Channel Block) 1 = TCHBLK/TCHCLK[8:1] pins output TCHCLK[8:1] (Transmit Channel Clock) Bit 0: Receive Channel Block/Clock Select (RCBCS). This bit controls the function of all eight RCHBLKn/RCHCLKn pins. 0 = RCHBLK/RCHCLK[8:1] pins output RCHBLK[8:1] (Receive Channel Block) 1 = RCHBLK/RCHCLK[8:1] pins output RCHCLK[8:1] (Receive Channel Clock) 121 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GTCR3 Global Transceiver Control Register 3 00F2h 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 TSSYNCIOSEL 0 0 TSYNCSEL 0 Bit # Name Default 7 -- 0 Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL) 0 = TSSYNCIO[8:1] are inputs on TSYNC/TSSYNCIO[8:1] pins 1 = TSSYNCIO[8:1] are outputs synchronous to BPCLK1. Bit 0: TSYNCn/TSSYNCIOn Pin Select (TSYNCSEL) 0 = TSYNCn is selected for TSYNC/TSSYNCIO[8:1] pins 1 = TSSYNCIOn is selected for TSYNC/TSSYNCIO[8:1] pins Note: If TSYNCn is selected, control of TSYNCn (I/O) is via the TIOCR register. TSSYNCIOn is normally selected when transmit elastic stores are enabled. 122 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GTCCR1 Global Transceiver Clock Control Register 1 00F3h 6 BPREFSEL2 Bit # Name Default 7 BPREFSEL3 5 BPREFSEL1 4 BPREFSEL0 3 BFREQSEL 2 FREQSEL 1 MPS1 0 MPS0 0 0 0 0 0 0 0 0 Bits 7 to 4: Backplane Clock Reference Selects (BPREFSEL[3:0]). These bits select which reference clock source will be used for BPCLK1 generation. The BPCLK1 can be generated from LIU's 1 to 8 recovered clocks, an external reference, or derivatives of MCLK input. This is shown in Table 10-13. See Figure 9-9 for additional information. Bit 3: Backplane Frequency Select (BFREQSEL). In conjunction with BPRFSEL[3:0], this bit identifies the reference clock frequency used by the DS26518 backplane clock generation circuit. Note that the setting of this bit should match the T1E1 selection for the LIU whose recovered clock is being used to generate the backplane clock. See Figure 9-9 for additional information. 0 = Backplane reference clock is 2.048MHz. 1 = Backplane reference clock is 1.544MHz. Bit 2: Frequency Selection (FREQSEL). In conjunction with the MPS[1:0] bits, this bit selects the external MCLK frequency of the signal input at the MCLK pin of the DS26518. 0 = The external master clock is 2.048MHz or multiple thereof. 1 = The external master clock is 1.544MHz or multiple thereof. Bits 1 and 0: Master Period Select 1 and 0 (MPS[1:0]). In conjunction with the FREQSEL bit, these bits select the external MCLK frequency of the signal input at the MCLK pin of the DS26518. This is shown in Table 10-12. Table 10-12. Master Clock Input Selection FREQSEL 0 0 0 0 1 1 1 1 MPS1 0 0 1 1 0 0 1 1 MPS0 0 1 0 1 0 1 0 1 MCLK (MHz 50ppm) 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352 123 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 10-13. Backplane Reference Clock Select BPREFSEL3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 BPREFSEL2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 BPREFSEL1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 BPREFSEL0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 BFREQSEL 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 REFERENCE CLOCK SOURCE 2.048MHz RCLK1 1.544MHz RCLK1 2.048MHz RCLK2 1.544MHz RCLK2 2.048MHz RCLK3 1.544MHz RCLK3 2.048MHz RCLK4 1.544MHz RCLK4 2.048MHz RCLK5 1.544MHz RCLK5 2.048MHz RCLK6 1.544MHz RCLK6 2.048MHz RCLK7 1.544MHz RCLK7 2.048MHz RCLK8 1.544MHz RCLK8 2.048MHz derived from MCLK. (REFCLKIO is an output.) 1.544MHz derived from MCLK. (REFCLKIO is an output.) 2.048MHz external clock input at REFCLKIO. (REFCLKIO is an input.) 1.544MHz external clock input at REFCLKIO. (REFCLKIO is an input.) 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 124 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GTCCR3 Global Transceiver Clock Control Register 3 00F4h 6 RSYSCLKSEL Bit # Name Default 7 -- 5 TSYSCLKSEL 0 0 0 4 TCLKSEL 0 3 CLKOSEL3 0 2 CLKOSEL2 0 1 CLKOSEL1 0 0 CLKOSEL0 0 Bit 6: RSYSCLKn Select (RSYSCLKSEL) 0 = Use RSYSCLKn pins for each receive system clock (Channels 1-8). 1 = Use BPCLK1 as the master clock for all eight receive system clocks (Channels 1-8). Bit 5: TSYSCLKn Select (TSYSCLKSEL) 0 = Use TSYSCLKn pins for each transmit system clock (Channels 1-8). 1 = Use BPCLK1 as the master clock for all eight transmit system clocks (Channels 1-8). Bit 4: TCLKn Select (TCLKSEL) 0 = Use TCLKn pins for each of the transmit clock (Channels 1-8). 1 = Use REFCLKIO as the master clock for all eight transmit clocks (Channels 1-8). Bits 3 to 0: Clock Out Frequency Select (CLKOSEL[3:0]. CLKO output pin will use MCLK (1.544MHz or 2.048MHz or scaled version) as its reference. The following table shows how to configure for each frequency. For best jitter performance use a 2.048MHz oscillator for MCLK. CLKOSEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLKO (kHz) 2048 4096 8192 16384 1544 3088 6176 12352 1536 3072 6144 12288 32 64 128 256 125 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GSRR1 Global LIU Software Reset Register 1 00F6h 6 -- Bit # Name Default 7 -- 5 -- 4 -- 3 -- 0 0 0 0 0 2 LRST 0 1 BRST 0 0 FRST 0 Bit 2: LIU Software Reset (LRST). LIU Channels 1-8 logic and registers are reset with a 0-to-1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal operation. 1 = Reset LIU channels 1-8. Bit 1: BERT Software Reset (BRST). BERT Channels 1-8 logic and registers are reset with a 0-to-1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal operation. 1 = Reset BERT channels 1-8. Bit 0: Framer Software Reset (FRST). Framers 1-8 to logic and registers are reset with a 0-to-1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal operation. 1 = Reset framers 1-8. Register Name: Register Description: Register Address: IDR Device Identification Register 00F8h 6 ID6 1 5 ID5 0 4 ID4 1 3 ID3 0 2 ID2 0 1 ID1 0 0 ID0 0 Bit # Name Default 7 ID7 1 Bits 7 to 3: Device ID (ID[7:3]). The upper five bits of the IDR are used to display the DS26518 ID. Table 10-14. Device ID Codes in this Product Family DEVICE DS26519 DS26518 DS26528 DS26524 DS26522 DS26521 ID7 1 1 0 0 0 0 ID6 1 1 1 1 1 1 ID5 0 0 0 1 1 1 ID4 1 1 1 0 0 1 ID3 1 0 1 0 1 0 Bits 2 to 0: Silicon Revision Bits (ID[2:0]). The lower three bits of the IDR are used to display a sequential number denoting the die revision of the chip. The initial silicon revision = "000" and is incremented with each silicon revision. This value is not the same as the two-character device revision on the top brand of the device. This is due to the fact that portions of the device assembly other than the silicon may change, causing the device revision increment on the brand without having a revision of the silicon. ID0 is the LSB of a decimal code that represents the chip revision. 126 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GFISR1 Global Framer Interrupt Status Register 1 00F9h 6 FIS7 0 5 FIS6 0 4 FIS5 0 3 FIS4 0 2 FIS3 0 1 FIS2 0 0 FIS1 0 Bit # Name Default 7 FIS8 0 The GFISR1 register reports the framer interrupt status for the T1/E1 framers of Channels 1 to 8. A logic one in the associated bit location indicates a framer has set its interrupt signal. Bit 7: Framer Interrupt Status 8 (FIS8) 0 = Framer 8 has not issued an interrupt. 1 = Framer 8 has issued an interrupt. Bit 6: Framer Interrupt Status 7 (FIS7) 0 = Framer 7 has not issued an interrupt. 1 = Framer 7 has issued an interrupt. Bit 5: Framer Interrupt Status 6 (FIS6) 0 = Framer 6 has not issued an interrupt. 1 = Framer 6 has issued an interrupt. Bit 4: Framer Interrupt Status 5 (FIS5) 0 = Framer 5 has not issued an interrupt. 1 = Framer 5 has issued an interrupt. Bit 3: Framer Interrupt Status 4 (FIS4) 0 = Framer 4 has not issued an interrupt. 1 = Framer 4 has issued an interrupt. Bit 2: Framer Interrupt Status 3 (FIS3) 0 = Framer 3 has not issued an interrupt. 1 = Framer 3 has issued an interrupt. Bit 1: Framer Interrupt Status 2 (FIS2) 0 = Framer 2 has not issued an interrupt. 1 = Framer 2 has issued an interrupt. Bit 0: Framer Interrupt Status 1 (FIS1) 0 = Framer 1 has not issued an interrupt. 1 = Framer 1 has issued an interrupt. 127 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GBISR1 Global BERT Interrupt Status Register 1 00FAh 6 BIS7 0 5 BIS6 0 4 BIS5 0 3 BIS4 0 2 BIS3 0 1 BIS2 0 0 BIS1 0 Bit # Name Default 7 BIS8 0 The GBISR1 register reports the interrupt status for the T1/E1 bit error rate testers (BERT) of Channels 1 to 8. A logic one in the associated bit location indicates a BERT has set its interrupt signal. Bit 7: BERT Interrupt Status 8 (BIS8) 0 = BERT 8 has not issued an interrupt. 1 = BERT 8 has issued an interrupt. Bit 6: BERT Interrupt Status 7 (BIS7) 0 = BERT 7 has not issued an interrupt. 1 = BERT 7 has issued an interrupt. Bit 5: BERT Interrupt Status 6 (BIS6) 0 = BERT 6 has not issued an interrupt. 1 = BERT 6 has issued an interrupt. Bit 4: BERT Interrupt Status 5 (BIS5) 0 = BERT 5 has not issued an interrupt. 1 = BERT 5 has issued an interrupt. Bit 3: BERT Interrupt Status 4 (BIS4) 0 = BERT 4 has not issued an interrupt. 1 = BERT 4 has issued an interrupt. Bit 2: BERT Interrupt Status 3 (BIS3) 0 = BERT 3 has not issued an interrupt. 1 = BERT 3 has issued an interrupt. Bit 1: BERT Interrupt Status 2 (BIS2) 0 = BERT 2 has not issued an interrupt. 1 = BERT 2 has issued an interrupt. Bit 0: BERT Interrupt Status 1 (BIS1) 0 = BERT 1 has not issued an interrupt. 1 = BERT 1 has issued an interrupt. 128 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GLISR1 Global LIU Interrupt Status Register 1 00FBh 6 LIS7 0 5 LIS6 0 4 LIS5 0 3 LIS4 0 2 LIS3 0 1 LIS2 0 0 LIS1 0 Bit # Name Default 7 LIS8 0 The GLISR1 register reports the LIU interrupt status for the T1/E1 LIUs of Channels 1 to 8. A logic one in the associated bit location indicates a LIU has set its interrupt signal. Bit 7: LIU Interrupt Status 8 (LIS8) 0 = LIU 8 has not issued an interrupt. 1 = LIU 8 has issued an interrupt. Bit 6: LIU Interrupt Status 7 (LIS7) 0 = LIU 7 has not issued an interrupt. 1 = LIU 7 has issued an interrupt. Bit 5: LIU Interrupt Status 6 (LIS6) 0 = LIU 6 has not issued an interrupt. 1 = LIU 6 has issued an interrupt. Bit 4: LIU Interrupt Status 5 (LIS5) 0 = LIU 5 has not issued an interrupt. 1 = LIU 5 has issued an interrupt. Bit 3: LIU Interrupt Status 4 (LIS4) 0 = LIU 4 has not issued an interrupt. 1 = LIU 4 has issued an interrupt. Bit 2: LIU Interrupt Status 3 (LIS3) 0 = LIU 3 has not issued an interrupt. 1 = LIU 3 has issued an interrupt. Bit 1: LIU Interrupt Status 2 (LIS2) 0 = LIU 2 has not issued an interrupt. 1 = LIU 2 has issued an interrupt. Bit 0: LIU Interrupt Status 1 (LIS1) 0 = LIU 1 has not issued an interrupt. 1 = LIU 1 has issued an interrupt. 129 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GFIMR1 Global Framer Interrupt Mask Register 1 00FCh 6 FIM7 0 5 FIM6 0 4 FIM5 0 3 FIM4 0 2 FIM3 0 1 FIM2 0 0 FIM1 0 Bit # Name Default 7 FIM8 0 Bit 7: Framer 8 Interrupt Mask (FIM8) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Framer 7 Interrupt Mask (FIM7) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: Framer 6 Interrupt Mask (FIM6) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Framer 5 Interrupt Mask (FIM5) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Framer 4 Interrupt Mask (FIM4) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Framer 3 Interrupt Mask (FIM3) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: Framer 2 Interrupt Mask (FIM2) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Framer 1 Interrupt Mask (FIM1) 0 = Interrupt masked. 1 = Interrupt enabled. 130 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GBIMR1 Global BERT Interrupt Mask Register 1 00FDh 6 BIM7 0 5 BIM6 0 4 BIM5 0 3 BIM4 0 2 BIM3 0 1 BIM2 0 0 BIM1 0 Bit # Name Default 7 BIM8 0 Bit 7: BERT Interrupt Mask 8 (BIM8) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: BERT Interrupt Mask 7 (BIM7) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: BERT Interrupt Mask 6 (BIM6) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: BERT Interrupt Mask 5 (BIM5) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: BERT Interrupt Mask 4 (BIM4) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: BERT Interrupt Mask 3 (BIM3) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: BERT Interrupt Mask 2 (BIM2) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: BERT Interrupt Mask 1 (BIM1) 0 = Interrupt masked. 1 = Interrupt enabled. 131 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GLIMR1 Global LIU Interrupt Mask Register 1 00FEh 6 LIM7 0 5 LIM6 0 4 LIM5 0 3 LIM4 0 2 LIM3 0 1 LIM2 0 0 LIM1 0 Bit # Name Default 7 LIM8 0 Bit 7: LIU Interrupt Mask 8 (LIM8) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: LIU Interrupt Mask 7 (LIM7) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: LIU Interrupt Mask 6 (LIM6) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: LIU Interrupt Mask 5 (LIM5) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: LIU Interrupt Mask 4 (LIM4) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: LIU Interrupt Mask 3 (LIM3) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: LIU Interrupt Mask 2 (LIM2) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: LIU Interrupt Mask 1 (LIM1) 0 = Interrupt masked. 1 = Interrupt enabled. 132 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.4 Framer Register Descriptions 10.4.1 Receive Register Descriptions See Table 10-3 for the complete framer register list. Register Name: Register Description: Register Address: RHC Receive HDLC Control Register 010h + (200h x (n - 1)) : where n = 1 to 8 6 RHR 0 5 RHMS 0 4 RHCS4 0 3 RHCS3 0 2 RHCS2 0 1 RHCS1 0 0 RHCS0 0 Bit # Name Default 7 RCRCD 0 Bit 7: Receive CRC-16 Display (RCRCD) 0 = Do not write received CRC-16 code to FIFO (default). 1 = Write received CRC-16 code to FIFO after last octet of packet. Bit 6: Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Note that this bit is a acknowledged reset. The host should set this bit and the DS26518 will clear it once the reset operation is complete. The DS26518 will complete the HDLC reset within 2 frames. 0 = Normal operation. 1 = Reset receive HDLC controller and flush the receive FIFO. Bit 5: Receive HDLC Mapping Select (RHMS) 0 = Receive HDLC assigned to channels. 1 = Receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode). Bits 4 to 0: Receive HDLC Channel Select 4 to 0 (RHCS[4:0]). These bits determine which DS0 is mapped to the HDLC controller when enabled with RHMS = 0. RHCS[4:0] = all 0s selects channel 1, RHCS[4:0] = all 1s selects channel 32 (E1). A change to the receive HDLC channel select is acknowledged only after a receive HDLC reset (RHR). 133 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RHBSE Receive HDLC Bit Suppress Register 011h + (200h x (n - 1)) : where n = 1 to 8 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0 Bit # Name Default 7 BSE8 0 Bit 7: Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 5: Receive Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used. Bit 4: Receive Channel Bit 5 Suppress (BSE5). Set to one to stop this bit from being used. Bit 3: Receive Channel Bit 4 Suppress (BSE4). Set to one to stop this bit from being used. Bit 2: Receive Channel Bit 3 Suppress (BSE3). Set to one to stop this bit from being used. Bit 1: Receive Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used. Bit 0: Receive Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used. 134 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RDS0SEL Receive Channel Monitor Select Register 012h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0 Bit # Name Default 7 -- 0 Bits 4 to 0: Receive Channel Monitor Bits (RCM[4:0]). RCM0 is the LSB of a 5-bit channel select that determines which receive DS0 channel data will appear in the RDS0M register. Register Name: Register Description: Register Address: RSIGC Receive-Signaling Control Register 013h + (200h x (n - 1)) : where n = 1 to 8 6 -- -- 0 5 -- -- 0 4 RFSA1 CASMS 0 3 -- -- 0 2 RSFF RSFF 0 1 RSFE RSFE 0 0 RSIE RSIE 0 Bit # Name Default 7 -- -- 0 Bit 4 (T1 Mode): Receive Force Signaling All Ones (RFSA1) 0 = Do not force robbed bit signaling to all ones. 1 = Force signaling bits to all ones on a per-channel basis according to the T1RSAOI1-3 registers. Bit 4 (E1 Mode): CAS Mode Select (CASMS) 0 = The DS26518 will initiate a resync when two consecutive multiframe alignment signals have been received with an error. 1 = The DS26518 will initiate a resync when two consecutive multiframe alignment signals have been received with an error, or 1 multiframe has been received with all the bits in time slot 16 in state 0. Alignment criteria is met when at least one bit in state 1 is present in the time slot 16 preceding the multiframe alignment signal first detected (G.732 alternate criteria). Bit 2: Receive-Signaling Force Freeze (RSFF). Freezes receive-side signaling at RSIGn (and RSERn if receivesignaling reinsertion is enabled); will override receive freeze enable (RFE). 0 = Do not force a freeze event. 1 = Force a freeze event. Bit 1: Receive-Signaling Freeze Enable (RSFE) 0 = No freezing of receive signaling data will occur. 1 = Allow freezing of receive signaling data at RSIGn (and RSERn if receive-signaling reinsertion is enabled). Bit 0: Receive-Signaling Integration Enable (RSIE) 0 = Signaling changes of state reported on any change in selected channels. 1 = Signaling must be stable for three multiframes in order for a change of state to be reported. 135 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RCR2 (T1 Mode) Receive Control Register 2 014h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 RSLC96 0 3 OOF2 0 2 OOF1 0 1 RAIIE 0 0 RRAIS 0 Bit # Name Default 7 -- 0 Bit 4: Receive SLC-96 Synchronizer Enable (RSLC96). See Section 9.9.4.4 for SLC-96 details. 0 = The SLC-96 synchronizer is disabled. 1 = The SLC-96 synchronizer is enabled. Bits 3 and 2: Out Of Frame Select Bits (OOF[2:1]) OOF2 0 0 1 1 OOF1 0 1 0 1 OUT OF FRAME CRITERIA 2/4 frame bits in error 2/5 frame bits in error 2/6 frame bits in error 2/6 frame bits in error Bit 1: Receive RAI Integration Enable (RAIIE). The ESF RAI indication can be interrupted for a period not to exceed 100ms per interruption (T1.403). In ESF mode, setting RAIIE will cause the RAI status from the DS26518 to be integrated for 200ms. 0= RAI detects when 16 consecutive patterns of 00FF appear in the FDL. RAI clears when 14 or fewer patterns of 00FF hex out of 16 possible appear in the FDL. 1= RAI detects when the condition has been present for greater than 200ms. RAI clears when the condition has been absent for greater than 200ms. Bit 0: Receive-Side Remote Alarm Select (RRAIS) 0 = Receive framer detects T1 remote alarm. D4--Zeros in bit 2 of all channels. ESF--00FF pattern in FDL. 1 = Receive Framer detects J1 Remote Alarm. D4--A one in the S-bit position of frame 12. ESF--all ones in FDL. 136 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1RSAIMR (E1 Mode Only) Receive Sa Bit Interrupt Mask Register 014h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 RSa4IM 0 3 RSa5IM 0 2 RSa6IM 0 1 RSa7IM 0 0 RSa8IM 0 Bit # Name Default 7 -- 0 Bit 4: Sa4 Change Detect Interrupt Mask (RSa4IM). This bit will enable the change detect interrupt for the Sa4 bits. Any change of state of the Sa4 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Sa5 Change Detect Interrupt Mask (RSa5IM). This bit will enable the change detect interrupt for the Sa5 bits. Any change of state of the Sa5 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Sa6 Change Detect Interrupt Mask (RSa6IM). This bit will enable the change detect interrupt for the Sa6 bits. Any change of state of the Sa6 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: Sa7 Change Detect Interrupt Mask (RSa7IM). This bit will enable the change detect interrupt for the Sa7 bits. Any change of state of the Sa7 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Sa8 Change Detect Interrupt Mask (RSa8IM). This bit will enable the change detect interrupt for the Sa8 bits. Any change of state of the Sa8 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt masked. 1 = Interrupt enabled. 137 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RBOCC (T1 Mode Only) Receive BOC Control Register 015h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 RBD1 0 4 RBD0 0 3 -- 0 2 RBF1 0 1 RBF0 0 0 -- 0 Bit # Name Default 7 RBR 0 Bit 7: Receive BOC Reset (RBR). The host should set this bit to force a reset of the BOC circuitry. Note that this is an acknowledged reset--that is, the host needs only to set the bit and the DS26518 will clear it once the reset operation is complete (less than 250s). Modifications to the RBF[1:0] and RBD[1:0] bits will not be applied to the BOC controller until a BOC reset has been completed. Bits 5 and 4: Receive BOC Disintegration Bits (RBD[1:0]). The BOC disintegration filter sets the number of message bits that must be received without a valid BOC to set the BC bit indicating that a valid BOC is no longer being received. RBD1 0 0 1 1 RBD0 0 1 0 1 CONSECUTIVE MESSAGE BITS FOR BOC CLEAR IDENTIFICATION 16 32 48 64 (See Note 1) Bits 2 and 1: Receive BOC Filter Bits (RBF[1:0). The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message. RBF1 0 0 1 1 RBF0 0 1 0 1 CONSECUTIVE BOC CODES FOR VALID SEQUENCE IDENTIFICATION None 3 5 7 (See Note 1) Note 1: The DS26518's BOC controller does not integrate and disintegrate concurrently. Therefore, if the maximum integration time and the maximum disintegration time are used together, BOC messages that repeat fewer than 11 times may not be detected. Register Name: Register Description: Register Address: RIDR1 to RIDR32 Receive Idle Code Definition Registers 1 to 32 020h to 03Fh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the code (this bit is transmitted last). Address 20h is for channel 1. Address 37h is for channel 24. Address 3Fh is for channel 32. RIDR25-RIDR32 are E1 mode only. 138 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only) Receive-Signaling All-Ones Insertion Registers 1 to 3 038h, 039h, 03Ah + (200h x (n - 1)) : where n = 1 to 8 Bit # Name (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 (LSB) 0 CH1 CH9 CH17 T1RSAOI1 T1RSAOI2 T1RSAOI3 Setting any of the CH[1:24] bits in the T1RSAOI1 to T1RSAOI3 registers will cause signaling data to be replaced with logic ones as reported on RSERn. The RSIGn signal will continue to report received signaling data. Note that this feature must be enabled with control bit RSIGC.4. Register Name: Register Description: Register Address: T1RDMWE1, T1RDMWE2, T1RDMWE3 T1 Receive Digital Milliwatt Enable Registers 1 to 3 03Ch, 03Dh, 03Eh + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 Bit # Name (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 T1RDMWE1 T1RDMWE2 T1RDMWE3 Bits 7 to 0: Receive Digital Milliwatt Enable for Channels 1 to 24 (CH[1:24]) 0 = Does not affect the receive data associated with this channel. 1 = Replace the receive data associated with this channel with digital milliwatt code. 139 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RS1 to RS16 Receive-Signaling Registers 1 to 16 040h to 04Fh + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH13-D CH14-D CH15-D CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D (LSB) 0 X CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH25-D CH26-D CH27-D CH28-D CH29-D CH30-D T1 Mode: Bit # Name (MSB) 7 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A (MSB) 7 0 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A CH13-A CH14-A CH15-A 6 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B 5 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C 4 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D 3 CH13-A CH14-A CH15-A CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A 2 CH13-B CH14-B CH15-B CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B 1 CH13-C CH14-C CH15-C CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 E1 Mode: Bit # Name 6 0 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B CH13-B CH14-B CH15-B 5 0 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH13-C CH14-C CH15-C 4 0 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-D CH14-D CH15-D 3 X CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH25-A CH26-A CH27-A CH28-A CH29-A CH30-A 2 Y CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH25-B CH26-B CH27-B CH28-B CH29-B CH30-B 1 X CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C CH25-C CH26-C CH27-C CH28-C CH29-C CH30-C RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4 framing mode, the framer will repeat the A and B signaling data in the C and D bit locations. Therefore, when the framer is operated in D4 framing mode, the user will need to retrieve the signaling bits every 1.5ms as opposed to 3ms for ESF mode. The receive-signaling registers are frozen and not updated during a loss of sync condition. They will contain the most recent signaling information before the "OOF" occurred. 140 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LCVCR1 Line Code Violation Count Register 1 050h + (200h x (n - 1)) : where n = 1 to 8 6 LCVC14 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCVC8 0 Bit # Name Default 7 LCVC15 0 Bits 7 to 0: Line Code Violation Counter Bits 15 to 8 (LCVC[15:8]). LCV15 is the MSB of the 16-bit code violation count. Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC7 0 LCVCR2 Line Code Violation Count Register 2 051h + (200h x (n - 1)) : where n = 1 to 8 6 LCVC6 0 5 LCVC5 0 4 LCVC4 0 3 LCVC3 0 2 LCVC2 0 1 LCVC1 0 0 LCVC0 0 Bits 7 to 0: Line Code Violation Counter Bits 7 to 0 (LCVC[7:0]). LCV0 is the LSB of the 16-bit code violation count. Register Name: Register Description: Register Address: PCVCR1 Path Code Violation Count Register 1 052h + (200h x (n - 1)) : where n = 1 to 8 6 PCVC14 0 5 PCVC13 0 4 PCVC12 0 3 PCVC11 0 2 PCVC10 0 1 PCVC9 0 0 PCVC8 0 Bit # Name Default 7 PCVC15 0 Bits 7 to 0: Path Code Violation Counter Bits 15 to 8 (PCVC[15:8]). PCVC15 is the MSB of the 16-bit path code violation count. Register Name: Register Description: Register Address: PCVCR2 Path Code Violation Count Register 2 053h + (200h x (n - 1)) : where n = 1 to 8 6 PCVC6 0 5 PCVC5 0 4 PCVC4 0 3 PCVC3 0 2 PCVC2 0 1 PCVC1 0 0 PCVC0 0 Bit # Name Default 7 PCVC7 0 Bits 7 to 0: Path Code Violation Counter Bits 7 to 0 (PCVC[7:0]). PCVC0 is the LSB of the 16-bit path code violation count. 141 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: FOSCR1 Frames Out of Sync Count Register 1 054h + (200h x (n - 1)) : where n = 1 to 8 6 FOS14 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0 Bit # Name Default 7 FOS15 0 Bits 7 to 0: Frames Out of Sync Counter Bits 15 to 8 (FOS[15:8]). FOS15 is the MSB of the 16-bit frames out of sync count. Register Name: Register Description: Register Address: FOSCR2 Frames Out of Sync Count Register 2 055h + (200h x (n - 1)) : where n = 1 to 8 6 FOS6 0 5 FOS5 0 4 FOS4 0 3 FOS3 0 2 FOS2 0 1 FOS1 0 0 FOS0 0 Bit # Name Default 7 FOS7 0 Bits 7 to 0: Frames Out of Sync Counter Bits 7 to 0 (FOS[7:0]). FOS0 is the LSB of the 16-bit frames out of sync count. Register Name: Register Description: Register Address: Bit # Name Default 7 EB15 0 E1EBCR1 (E1 Mode Only) E-Bit Count Register 1 056h + (200h x (n - 1)) : where n = 1 to 8 6 EB14 0 5 EB13 0 4 EB12 0 3 EB11 0 2 EB10 0 1 EB9 0 0 EB8 0 Bits 7 to 0: E-Bit Counter Bits 15 to 8 (EB[15:8]). EB15 is the MSB of the 16-bit E-bit count. Register Name: Register Description: Register Address: Bit # Name Default 7 EB7 0 E1EBCR2 (E1 Mode Only) E-Bit Count Register 2 057h + (200h x (n - 1)) : where n = 1 to 8 6 EB6 0 5 EB5 0 4 EB4 0 3 EB3 0 2 EB2 0 1 EB1 0 0 EB0 0 Bits 7 to 0: E-Bit Counter Bits 7 to 0 (EB[7:0]). EB0 is the LSB of the 16-bit E-bit count. 142 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 FEACR15 0 FEACR1 Error Count A Register 1 058h + (200h x (n - 1)) : where n = 1 to 8 6 FEACR14 0 5 FEACR13 0 4 FEACR12 0 3 FEACR11 0 2 FEACR10 0 1 FEACR9 0 0 FEACR8 0 Bits 7 to 0: Error Count A Register 1 Bits 15 to 8 (FEACR[15:8]). FEACR15 is the MSB of the 16-bit Far End A Counter. Register Name: Register Description: Register Address: Bit # Name Default 7 FEACR7 0 FEACR2 Error Count A Register 2 059h + (200h x (n - 1)) : where n = 1 to 8 6 FEACR6 0 5 FEACR5 0 4 FEACR4 0 3 FEACR3 0 2 FEACR2 0 1 FEACR1 0 0 FEACR0 0 Bits 7 to 0: Error Count A Register 2 Bits 7 to 0 (FEACR[7:0]). FEACR0 is the LSB of the 16-bit Far End A Counter. Register Name: Register Description: Register Address: Bit # Name Default 7 FEBCR15 0 FEBCR1 Error Count B Register 1 05Ah + (200h x (n - 1)) : where n = 1 to 8 6 FEBCR14 0 5 FEBCR13 0 4 FEBCR12 0 3 FEBCR11 0 2 FEBCR10 0 1 FEBCR9 0 0 FEBCR8 0 Bits 7 to 0: Error Count B Register 1 Bits 15 to 8 (FEBCR[15:8]). FEBCR15 is the MSB of the 16-bit Far End Error B Counter. Register Name: Register Description: Register Address: Bit # Name Default 7 FEBCR7 0 FEBCR2 Error Count B Register 2 05Bh + (200h x (n - 1)) : where n = 1 to 8 6 FEBCR6 0 5 FEBCR5 0 4 FEBCR4 0 3 FEBCR3 0 2 FEBCR2 0 1 FEBCR1 0 0 FEBCR0 0 Bits 7 to 0: Error Count B Register 2 Bits 7 to 0 (FEBCR[7:0]). FEBCR0 is the LSB of the 16-bit Far End Error B Counter. 143 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RDS0M Receive DS0 Monitor Register 060h + (200h x (n - 1)) : where n = 1 to 8 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bit # Name Default 7 B1 0 Bits 7 to 0: Receive DS0 Channel Bits (B[1:8]). Receive channel data that has been selected by the Receive Channel Monitor Select Register (RDS0SEL). B8 is the LSB of the DS0 channel (last bit to be received). 144 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RFDL (T1 Mode) Receive FDL Register 062h + (200h x (n - 1)) : where n = 1 to 8 6 RFDL6 0 5 RFDL5 0 4 RFDL4 0 3 RFDL3 0 2 RFDL2 0 1 RFDL1 0 0 RFDL0 0 Bit # Name Default 7 RFDL7 0 Note: This register has an alternate definition for E1 mode. See E1RRTS7. Bit 7: Receive FDL Bit 7 (RFDL7). MSB of the received FDL code. Bit 6: Receive FDL Bit 6 (RFDL6). Bit 5: Receive FDL Bit 5 (RFDL5). Bit 4: Receive FDL Bit 4 (RFDL4). Bit 3: Receive FDL Bit 3 (RFDL3). Bit 2: Receive FDL Bit 2 (RFDL2). Bit 1: Receive FDL Bit 1 (RFDL1). Bit 0: Receive FDL Bit 0 (RFDL0). LSB of the received FDL code. Register Name: Register Description: Register Address: E1RRTS7 (E1 Mode) Receive Real-Time Status Register 7 062h + (200h x (n - 1)) : where n = 1 to 8 6 CSC4 0 5 CSC3 0 4 CSC2 0 3 CSC0 0 2 CRC4SA 0 1 CASSA 0 0 FASSA 0 Bit # Name Default 7 CSC5 0 Note: This register has an alternate definition for T1 mode. See T1RFDL. All bits in this register are real-time (not latched). Bits 7 to 3: CRC-4 Sync Counter Bits (CSC[5:2] and CSC0). The CRC-4 sync counter increments each time the 8ms CRC-4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC-4 level. The counter can also be cleared by disabling the CRC-4 mode (RCR1.3 = 0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC-4 level. ITU-T G.706 suggests that if synchronization at the CRC-4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. The CRC-4 sync counter will saturate (not rollover). CSC0 is the LSB of the 6-bit counter. (Note: CSC1 is omitted to allow resolution to > 400ms using 5 bits.) Bit 2: CRC-4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC-4 MF alignment word. Bit 1: CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word. Bit 0: FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level. 145 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RBOC (T1 Mode) Receive BOC Register 63h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0 Bit # Name Default 7 -- 0 Bit 5: BOC Bit 5 (RBOC5) Bit 4: BOC Bit 4 (RBOC4) Bit 3: BOC Bit 3 (RBOC3) Bit 2: BOC Bit 2 (RBOC2) Bit 1: BOC Bit 1 (RBOC1) Bit 0: BOC Bit 0 (RBOC0) The T1RBOC register always contains the last valid BOC received. The Receive FDL Register (T1RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, RFDL updates on multiframe boundaries and reports the six Fs bits in RFDL[5:0]. 146 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RSLC1, T1RSLC2, T1RSLC3 (T1 Mode) Receive SLC96 Data Link Registers 064h, 065h, 066h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 C1 C9 M3 Bit # Name (MSB) 7 C8 M2 S=1 6 C7 M1 S4 5 C6 S=0 S3 4 C5 S=1 S2 3 C4 S=0 S1 2 C3 C11 A2 1 C2 C10 A1 T1RSLC1 T1RSLC2 T1RSLC3 Note: These registers have an alternate definition for E1 mode. See E1RAF, E1RNAF, and E1RsiAF. Register Name: Register Description: Register Address: E1RAF (E1 Mode) E1 Receive Align Frame Register 064h + (200h x (n - 1)) : where n = 1 to 8 6 0 0 5 0 0 4 1 0 3 1 0 2 0 0 1 1 0 0 1 0 Bit # Name Default 7 Si 0 Note: This register has an alternate definition for T1 mode. See T1RSLC1. Bit 7: International Bit (Si) Bit 6: Frame Alignment Signal Bit (0) Bit 5: Frame Alignment Signal Bit (0) Bit 4: Frame Alignment Signal Bit (1) Bit 3: Frame Alignment Signal Bit (1) Bit 2: Frame Alignment Signal Bit (0) Bit 1: Frame Alignment Signal Bit (1) Bit 0: Frame Alignment Signal Bit (1) 147 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1RNAF (E1 Mode) E1 Receive Non-Align Frame Register 065h + (200h x (n - 1)) : where n = 1 to 8 6 1 0 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit # Name Default 7 Si 0 Note: This register has an alternate definition for T1 mode. See T1RSLC2. Bit 7: International Bit (Si) Bit 6: Frame Non-Alignment Signal Bit (1) Bit 5: Remote Alarm (A) Bit 4: Additional Bit 4 (Sa4) Bit 3: Additional Bit 5 (Sa5) Bit 2: Additional Bit 6 (Sa6) Bit 1: Additional Bit 7 (Sa7) Bit 0: Additional Bit 8 (Sa8) Register Name: Register Description: Register Address: E1RsiAF (E1 Mode) Received Si Bits of the Align Frame 066h + (200h x (n - 1)) : where n = 1 to 8 6 SiF12 0 5 SiF10 0 4 SiF8 0 3 SiF6 0 2 SiF4 0 1 SiF2 0 0 SiF0 0 Bit # Name Default 7 SiF14 0 Note: This register has an alternate definition for T1 mode. See T1RSLC3. Bit 7: Si Bit of Frame 14 (SiF14) Bit 6: Si Bit of Frame 12 (SiF12) Bit 5: Si Bit of Frame 10 (SiF10) Bit 4: Si Bit of Frame 8 (SiF8) Bit 3: Si Bit of Frame 6 (SiF6) Bit 2: Si Bit of Frame 4 (SiF4) Bit 1: Si Bit of Frame 2 (SiF2) Bit 0: Si Bit of Frame 0 (SiF0) 148 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1RSiNAF (E1 Mode Only) Receive Si Bits of the Non-Align Frame Register 067h + (200h x (n - 1)) : where n = 1 to 8 6 SiF13 0 5 SiF11 0 4 SiF9 0 3 SiF7 0 2 SiF5 0 1 SiF3 0 0 SiF1 0 Bit # Name Default 7 SiF15 0 Bit 7: Si Bit of Frame 15 (SiF15) Bit 6: Si Bit of Frame 13 (SiF13) Bit 5: Si Bit of Frame 11 (SiF11) Bit 4: Si Bit of Frame 9 (SiF9) Bit 3: Si Bit of Frame 7 (SiF7) Bit 2: Si Bit of Frame 5 (SiF5) Bit 1: Si Bit of Frame 3 (SiF3) Bit 0: Si Bit of Frame 1 (SiF1) Register Name: Register Description: Register Address: E1RRA (E1 Mode Only) Receive Remote Alarm Register 068h + (200h x (n - 1)) : where n = 1 to 8 6 RRAF13 0 5 RRAF11 0 4 RRAF9 0 3 RRAF7 0 2 RRAF5 0 1 RRAF3 0 0 RRAF1 0 Bit # Name Default 7 RRAF15 0 Bit 7: Remote Alarm Bit of Frame 15 (RRAF15) Bit 6: Remote Alarm Bit of Frame 13 (RRAF13) Bit 5: Remote Alarm Bit of Frame 11 (RRAF11) Bit 4: Remote Alarm Bit of Frame 9 (RRAF9) Bit 3: Remote Alarm Bit of Frame 7 (RRAF7) Bit 2: Remote Alarm Bit of Frame 5 (RRAF5) Bit 1: Remote Alarm Bit of Frame 3 (RRAF3) Bit 0: Remote Alarm Bit of Frame 1 (RRAF1) 149 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1RSa4 (E1 Mode Only) Received Sa4 Bits Register 069h + (200h x (n - 1)) : where n = 1 to 8 6 RSa4F13 0 5 RSa4F11 0 4 RSa4F9 0 3 RSa4F7 0 2 RSa4F5 0 1 RSa4F3 0 0 RSa4F1 0 Bit # Name Default 7 RSa4F15 0 Bit 7: Sa4 Bit of Frame 15 (RSa4F15) Bit 6: Sa4 Bit of Frame 13 (RSa4F13) Bit 5: Sa4 Bit of Frame 11 (RSa4F11) Bit 4: Sa4 Bit of Frame 9 (RSa4F9) Bit 3: Sa4 Bit of Frame 7 (RSa4F7) Bit 2: Sa4 Bit of Frame 5 (RSa4F5) Bit 1: Sa4 Bit of Frame 3 (RSa4F3) Bit 0: Sa4 Bit of Frame 1 (RSa4F1) Register Name: Register Description: Register Address: E1RSa5 (E1 Mode Only) Received Sa5 Bits Register 06Ah + (200h x (n - 1)) : where n = 1 to 8 6 RSa5F13 0 5 RSa5F11 0 4 RSa5F9 0 3 RSa5F7 0 2 RSa5F5 0 1 RSa5F3 0 0 RSa5F1 0 Bit # Name Default 7 RSa5F15 0 Bit 7: Sa5 Bit of Frame 15 (RSa5F15) Bit 6: Sa5 Bit of Frame 13 (RSa5F13) Bit 5: Sa5 Bit of Frame 11 (RSa5F11) Bit 4: Sa5 Bit of Frame 9 (RSa5F9) Bit 3: Sa5 Bit of Frame 7 (RSa5F7) Bit 2: Sa5 Bit of Frame 5 (RSa5F5) Bit 1: Sa5 Bit of Frame 3 (RSa5F3) Bit 0: Sa5 Bit of Frame 1 (RSa5F1) 150 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1RSa6 (E1 Mode Only) Received Sa6 Bits Register 06Bh + (200h x (n - 1)) : where n = 1 to 8 6 RSa6F13 0 5 RSa6F11 0 4 RSa6F9 0 3 RSa6F7 0 2 RSa6F5 0 1 RSa6F3 0 0 RSa6F1 0 Bit # Name Default 7 RSa6F15 0 Bit 7: Sa6 Bit of Frame 15 (RSa6F15) Bit 6: Sa6 Bit of Frame 13 (RSa6F13) Bit 5: Sa6 Bit of Frame 11 (RSa6F11) Bit 4: Sa6 Bit of Frame 9 (RSa6F9) Bit 3: Sa6 Bit of Frame 7 (RSa6F7) Bit 2: Sa6 Bit of Frame 5 (RSa6F5) Bit 1: Sa6 Bit of Frame 3 (RSa6F3) Bit 0: Sa6 Bit of Frame 1 (RSa6F1) Register Name: Register Description: Register Address: E1RSa7 (E1 Mode Only) Received Sa7 Bits Register 06Ch + (200h x (n - 1)) : where n = 1 to 8 6 RSa7F13 0 5 RSa7F11 0 4 RSa7F9 0 3 RSa7F7 0 2 RSa7F5 0 1 RSa7F3 0 0 RSa7F1 0 Bit # Name Default 7 RSa7F15 0 Bit 7: Sa7 Bit of Frame 15 (RSa4F15) Bit 6: Sa7 Bit of Frame 13 (RSa7F13) Bit 5: Sa7 Bit of Frame 11 (RSa7F11) Bit 4: Sa7 Bit of Frame 9 (RSa7F9) Bit 3: Sa7 Bit of Frame 7 (RSa7F7) Bit 2: Sa7 Bit of Frame 5 (RSa7F5) Bit 1: Sa7 Bit of Frame 3 (RSa7F3) Bit 0: Sa7 Bit of Frame 1 (RSa7F1) 151 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1RSa8 (E1 Mode Only) Received Sa8 Bits Register 06Dh + (200h x (n - 1)) : where n = 1 to 8 6 RSa8F13 0 5 RSa8F11 0 4 RSa8F9 0 3 RSa8F7 0 2 RSa8F5 0 1 RSa8F3 0 0 RSa8F1 0 Bit # Name Default 7 RSa8F15 0 Bit 7: Sa8 Bit of Frame 15 (RSa8F15) Bit 6: Sa8 Bit of Frame 13 (RSa8F13) Bit 5: Sa8 Bit of Frame 11 (RSa8F11) Bit 4: Sa8 Bit of Frame 9 (RSa8F9) Bit 3: Sa8 Bit of Frame 7 (RSa8F7) Bit 2: Sa8 Bit of Frame 5 (RSa8F5) Bit 1: Sa8 Bit of Frame 3 (RSa8F3) Bit 0: Sa8 Bit of Frame 1 (RSa8F1) Register Name: Register Description: Register Address: SaBITS Received SaX Bits Register 06Eh + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit # Name Default 7 -- 0 This register indicates the last received SaX bit. This can be used in conjunction with the RLS7 register to determine which SaX bits have changed. The user can program which Sa bit positions should be monitored via the E1RSAIMR register, and when a change is detected through an interrupt in RLS7.0, the user can determine which bit has changed by reading this register and comparing it with previous known values. Bit 4: Last Received Sa4 Bit (Sa4) Bit 3: Last Received Sa5 Bit (Sa4) Bit 2: Last Received Sa6 Bit (Sa5) Bit 1: Last Received Sa7 Bit (Sa7) Bit 0: Last Received Sa8 Bit (Sa8) 152 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Sa6CODE Received Sa6 Codeword Register 06Fh + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 Sa6n 0 2 Sa6n 0 1 Sa6n 0 0 Sa6n 0 Bit # Name Default 7 -- 0 This register will report the received Sa6 codeword per ETS 300 233. The bits are monitored on a submultiframe asynchronous basis, so the pattern reported could be one of multiple patterns that would represent a valid codeword. The table below indicates which patterns reported in this register correspond to a given valid Sa6 codeword. Bits 3 to 0: Sa6 Codeword Bit (Sa6n) POSSIBLE REPORTED VALID Sa6 CODE PATTERNS Sa6_8 1000, 0100, 0010, 0001 Sa6_A 1010, 0101 Sa6_C 110, 0110, 0011, 1001 Sa6_E 1110, 0111, 1011, 1101 Sa6_F 1111 Register Name: Register Description: Register Address: RMMR Receive Master Mode Register 080h + (200h x (n - 1)) : where n = 1 to 8 6 INIT_DONE 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 SFTRST 0 0 T1/E1 0 Bit # Name Default 7 FRM_EN 0 Bit 7: Framer Enable (FRM_EN). This bit must be set to the desired state before writing INIT_DONE. 0 = Framer disabled--held in low-power state. 1 = Framer enabled--all features active. Bit 6: Initialization Done (INIT_DONE). The user must set this bit once he has written the configuration registers. The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the DS26518 will check the FRM_EN bit and, if enabled, will begin operation based on the initial configuration. Bit 1: Soft Reset (SFTRST). Level sensitive "soft" reset. Should be taken high, then low to reset the receiver. 0 = Normal operation. 1 = Reset the receiver. Note: This reset does not clear the registers. Bit 0: Receiver T1/E1 Mode Select (T1/E1). Sets operating mode for receiver only! This bit must be set to the desired state before writing INIT_DONE. 0 = T1 operation. 1 = E1 operation. 153 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RCR1 (T1 Mode) Receive Control Register 1 081h + (200h x (n - 1)) : where n = 1 to 8 6 RB8ZS 0 5 RFM 0 4 ARC 0 3 SYNCC 0 2 RJC 0 1 SYNCE 0 0 RESYNC 0 Bit # Name Default 7 SYNCT 0 Note: This register has an alternate definition for E1 mode. See RCR1. Bit 7: Sync Time (SYNCT) 0 = Qualify 10 bits. 1 = Qualify 24 bits. Bit 6: Receive B8ZS Enable (RB8ZS) 0 = B8ZS disabled. 1 = B8ZS enabled. Bit 5: Receive Frame Mode Select (RFM) 0 = ESF framing mode. 1 = D4 framing mode. Bit 4: Auto Resync Criteria (ARC) 0 = Resync on OOF or LOS event. 1 = Resync on OOF only. Bit 3: Sync Criteria (SYNCC) In D4 Framing Mode: 0 = Search for Ft pattern, then search for Fs pattern. 1 = Cross couple Ft and Fs pattern. In ESF Framing Mode: 0 = Search for FPS pattern only. 1 = Search for FPS and verify with CRC-6. Bit 2: Receive Japanese CRC-6 Enable (RJC) 0 = Use ANSI:AT&T:ITU-T CRC-6 calculation (normal operation). 1 = Use Japanese standard JT-G704 CRC-6 calculation. Bit 1: Sync Enable (SYNCE) 0 = Auto resync enabled. 1 = Auto resync disabled. Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is initiated. Must be cleared and set again for a subsequent resync. 154 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RCR1 (E1 Mode) Receive Control Register 1 081h + (200h x (n - 1)) : where n = 1 to 8 6 RHDB3 0 5 RSIGM 0 4 RG802 0 3 RCRC4 0 2 FRC 0 1 SYNCE 0 0 RESYNC 0 Bit # Name Default 7 -- 0 Note: This register has an alternate definition for T1 mode. See RCR1. Bit 6: Receive HDB3 Enable (RHDB3) 0 = HDB3 disabled. 1 = HDB3 enabled (decoded per O.162). Bit 5: Receive Signaling Mode Select (RSIGM) 0 = CAS signaling mode. 1 = CCS signaling mode. Bit 4: Receive G.802 Enable (RG802). See Figure 11-30 for details. 0 = Do not force RCHBLKn high during bit 1 of time slot 26. 1 = Force RCHBLKn high during bit 1 of time slot 26. Bit 3: Receive CRC-4 Enable (RCRC4) 0 = CRC-4 disabled. 1 = CRC-4 enabled. Bit 2: Frame Resync Criteria (FRC) 0 = Resync if FAS received in error three consecutive times. 1 = Resync if FAS or bit 2 of non-FAS is received in error three consecutive times. Bit 1: Sync Enable (SYNCE) 0 = Auto resync enabled. 1 = Auto resync disabled. Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is initiated. Must be cleared and set again for a subsequent resync. 155 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RIBCC (T1 Mode) Receive In-Band Code Control Register 082h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 RUP2 0 4 RUP1 0 3 RUP0 0 2 RDN2 0 1 RDN1 0 0 RDN0 0 Bit # Name Default 7 -- 0 Note: This register has an alternate definition for E1 mode. See E1RCR2. Bits 5 to 3: Receive Up Code Length Definition Bits (RUP[2:0]) RUP2 0 0 0 0 1 1 1 1 RUP1 0 0 1 1 0 0 1 1 RUP0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 : 16 bits Bits 2 to 0: Receive Down Code Length Definition Bits (RDN[2:0]) RDN2 0 0 0 0 1 1 1 1 RDN1 0 0 1 1 0 0 1 1 RDN0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 : 16 bits Register Name: Register Description: Register Address: E1RCR2 (E1 Mode) Receive Control Register 2 082h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 RLOSA 0 Bit # Name Default 7 -- 0 Note: This register has an alternate definition for T1 mode. See T1RIBCC. Bit 0: Receive Loss of Signal Alternate Criteria (RLOSA). Defines the criteria for a loss of signal condition. 0 = LOS declared upon 255 consecutive zeros (125s). 1 = LOS declared upon 2048 consecutive zeros (1ms). 156 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RCR3 Receive Control Register 3 083h + (200h x (n - 1)) : where n = 1 to 8 6 uALAW 0 5 RSERC 0 4 BINV1 0 3 BINV0 0 2 -- 0 1 PLB 0 0 FLB 0 Bit # Name Default 7 -- 0 Bit 6: u-Law or A-Law Digital Milliwatt Code Select (uALAW) 0 = u-law code is inserted based on T1RDMWE1-3 or E1RDMWE1-4 registers. 1 = A-law code is inserted based on T1RDMWE1-3 or E1RDMWE1-4 registers. Bit 5: RSERn Control (RSERC) 0 = Allow RSERn to output data as received under all conditions (normal operation). 1 = Force RSERn to one under loss of frame alignment conditions. Bits 4 and 3: Receive Bit Inversion (BINV[1:0]) 00 = No inversion. 01 = Invert framing. 10 = Invert signaling. 11 = Invert payload. Bit 1: Payload Loopback (PLB) 0 = Loopback disabled. 1 = Loopback enabled. When PLB is enabled, the following will occur: 1) 2) 3) 4) Data will be transmitted on TTIPn and TRINGn synchronous with RCLKn instead of TCLKn. All of the receive-side signals will continue to operate normally. The TCHCLKn and TCHBLKn signals are forced low. Data at the TSERn, TDATAn, and TSIGn pins is ignored. In a PLB situation, the DS26518 will loop the 192 bits (248 for E1) of payload data (with BPVs corrected) from the receive section back to the transmit section. The transmitter will follow the frame alignment provided by the receiver. The receive frame boundary is automatically fed into the transmit section, such that the transmit frame position is locked to the receiver (i.e., TSYNCn is sourced from RSYNCn). The FPS framing pattern, CRC-6 calculation, and the FDL bits (FAS word, Si, Sa, E bits, and CRC-4 for E1) are not looped back, they are reinserted by the DS26518 (i.e., the transmit section will modify the payload as if it was input at TSERn). Bit 0: Framer Loopback (FLB) 0 = loopback disabled 1 = loopback enabled This loopback is useful in testing and debugging applications. In FLB, the DS26518 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1) (T1 mode) an unframed all-ones code will be transmitted at TTIPn and TRINGn. (E1 mode) normal data will be transmitted at TTIPn and TRINGn. 2) Data at RTIPn and RRINGn will be ignored. 3) All receive-side signals will take on timing synchronous with TCLKn instead of RCLKn. Note that it is not acceptable to have RCLKn tied to TCLKn during this loopback because this will cause an unstable condition. 157 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1RDMWE1, E1RDMWE2, E1RDMWE3, E1RDMWE4 E1 Receive Digital Milliwatt Enable Registers 1 to 4 000h, 001h, 002h, 003h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 E1RDMWE1 E1RDMWE2 E1RDMWE3 E1RDMWE4 Bits 7 to 0: E1 Receive Digital Milliwatt Enable for Channels 1 to 32 (CH[1:32]) 0 = Do not affect the receive data associated with this channel. 1 = Replace the receive data associated with this channel with digital milliwatt code. Register Name: Register Description: Register Address: TDMWE1, TDMWE2, TDMWE3, TDMWE4 (T1 and E1 Modes) Transmit Digital Milliwatt Enable Registers 1 to 4 100h, 101h, 102h, 103h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 TDMWE1 TDMWE2 TDMWE3 TDMWE4 Bits 7 to 0: Transmit Digital Milliwatt Enable for Channels 1 to 32 (CH[1:32]) 0 = Do not affect the transmit data associated with this channel. 1 = Replace the transmit data associated with this channel with digital milliwatt code. 158 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIOCR Receive I/O Configuration Register 084h + (200h x (n - 1)) : where n = 1 to 8 6 RSYNCINV RSYNCINV Bit # Name Default 7 RCLKINV RCLKINV 5 H100EN H100EN 4 RSCLKM RSCLKM 0 0 0 0 3 RSMS -- 0 2 RSIO RSIO 1 1 RSMS2 RSMS2 0 0 RSMS1 RSMS1 0 Bit 7: RCLKn Invert (RCLKINV) 0 = No inversion. 1 = Invert RCLKn. Bit 6: RSYNCn Invert (RSYNCINV) 0 = No inversion. 1 = Invert RSYNCn as either input or output. Bit 5: H.100 Sync Mode (H100EN). See Section 9.8.3 for more information. 0 = Normal operation. 1 = RSYNCn and TSSYNCIOn signals are shifted. Bit 4: RSYSCLKn Mode Select (RSCLKM) 0 = If RSYSCLKn is 1.544MHz. 1 = If RSYSCLKn is 2.048MHz or IBO enabled. Bit 3: RSYNCn Multiframe Skip Control (RSMS) (T1 Mode Only). Useful in framing format conversions from D4 to ESF. This function is not available when the receive-side elastic store is enabled. RSYNCn must be set to output multiframe pulses. 0 = RSYNCn will output a pulse at every multiframe. 1 = RSYNCn will output a pulse at every other multiframe. Bit 2: RSYNCn I/O Select (RSIO). (Note: This bit must be set to zero when elastic store is disabled.) The default value for this bit is a logic 1 so that the default state of RSYNCn is as an input. 0 = RSYNCn is an output. 1 = RSYNCn is an input (only valid if elastic store enabled). Bit 1: RSYNCn Mode Select 2 (RSMS2) T1: RSYNCn pin must be programmed in the output frame mode. 0 = do not pulse double wide in signaling frames. 1 = do pulse double wide in signaling frames. E1: RSYNCn pin must be programmed in the output multiframe mode. 0 = RSYNCn outputs CAS multiframe boundaries. 1 = RSYNCn outputs CRC-4 multiframe boundaries. In E1 mode, RSMS2 also selects which multiframe signal is available at the RMSYNCn pin, regardless of the configuration for RSYNCn. When RSMS2 = 0, RMSYNCn outputs CAS multiframe boundaries; when RSMS2 = 1, RMSYNCn outputs CRC-4 multiframe boundaries. Bit 0: RSYNC Mode Select 1 (RSMS1). Selects frame or multiframe pulse when RSYNCn pin is in output mode. In input mode (elastic store must be enabled) multiframe mode is only useful when receive signaling reinsertion is enabled. 0 = Frame mode. 1 = Multiframe mode. 159 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RESCR Receive Elastic Store Control Register 085h + (200h x (n - 1)) : where n = 1 to 8 6 RGCLKEN Bit # Name Default 7 RDATFMT 0 0 5 -- 0 4 RSZS 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0 Bit 7: Receive Channel Data Format (RDATFMT) 0 = 64kbps (data contained in all 8 bits). 1 = 56kbps (data contained in 7 out of the 8 bits). Bit 6: Receive Gapped Clock Enable (RGCLKEN) 0 = RCHCLKn functions normally. 1 = Enable gapped bit clock output on RCHCLKn. Note: RGPCKEN and RDATFMT are not associated with the elastic store and will be explained in the fractional support section. Bit 4: Receive Slip Zone Select (RSZS). This bit determines the minimum distance allowed between the elastic store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1 conversion applications. 0 = Force a slip at 9 bytes or less of separation (used for clustered blank channels). 1 = Force a slip at 2 bytes or less of separation (used for distributed blank channels and minimum delay mode). Bit 3: Receive Elastic Store Align (RESALGN). Setting this bit from a zero to a one will force the receive elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after RSYSCLKn has been applied and is stable. Must be cleared and set again for a subsequent align. Bit 2: Receive Elastic Store Reset (RESR). Setting this bit from a zero to a one will force the read pointer into the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will move back to opposite frames. Should be toggled after RSYSCLKn has been applied and is stable. Do not leave this bit set HIGH. Bit 1: Receive Elastic Store Minimum Delay Mode (RESMDM) 0 = Elastic stores operate at full two-frame depth. 1 = Elastic stores operate at 32-bit depth. Bit 0: Receive Elastic Store Enable (RESE) 0 = Elastic store is bypassed. 1 = Elastic store is enabled. 160 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: ERCNT Error Counter Configuration Register 086h + (200h x (n - 1)) : where n = 1 to 8 6 MCUS MCUS 0 5 MECU MECU 0 4 ECUS ECUS 0 3 EAMS EAMS 0 2 FSBE -- 0 1 MOSCRF Bit # Name Default 7 1SECS 1SECS 0 -- 0 0 LCVCRF LCVCRF 0 Bit 7: One-Second Select (1SECS). This bit allows for synchronization of the error counter updates between multiple ports. When ERCNT.3 = 0, setting this bit (on a specific framer) will update the framer's error counters on the transition of the one-second timer from framer 1. Note that this bit should always be clear for framer 1. 0 = Use the one-second timer that is internal to the framer. 1 = Use the one-second timer from framer 1 to latch updates. Bit 6 : Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS, this bit can be used to allow the incoming LATCH_CNT signal to latch all counters. Useful for synchronously latching counters of multiple DS26518 cores located on the same die. 0 = MECU is used to manually latch counters. 1 = Counters are latched on the rising edge of the LATCH_CNT signal. Bit 5: Manual Error Counter Update (MECU). When enabled by ERCNT.3, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a minimum of 250s before reading the error count registers to allow for proper update. Bit 4: Error Counter Update Select (ECUS) T1 mode: 0 = Update error counters once a second. 1 = Update error counters every 42ms (333 frames). E1 mode: 0 = Update error counters once a second. 1 = Update error counters every 62.5ms (500 frames). Bit 3: Error Accumulation Mode Select (EAMS) 0 = Automatic updating of error counters enabled. The state of ERCNT.4 determines accumulation time (timed update). 1 = User toggling of ERCNT.5 determines accumulation time (manual update). Bit 2: PCVCR Fs-Bit Error Report Enable (FSBE) (T1 Mode Only) 0 = Do not report bit errors in Fs-bit position; only Ft-bit position. 1 = Report bit errors in Fs-bit position as well as Ft-bit position. Bit 1: Multiframe Out of Sync Count Register Function Select (MOSCRF) (T1 Mode Only) 0 = Count errors in the framing bit position. 1 = Count the number of multiframes out of sync. Bit 0: T1 Line Code Violation Count Register Function Select (LCVCRF) 0 = Do not count excessive zeros. 1 = Count excessive zeros. 161 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RHFC Receive HDLC FIFO Control Register 087h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 RFHWM1 0 0 RFHWM0 0 Bit # Name Default 7 -- 0 Bits 1 and 0 : Receive FIFO High Watermark Select (RFHWM[1:0] RFHWM1 0 0 1 1 RFHWM0 0 1 0 1 Receive FIFO Watermark 4 bytes 16 bytes 32 bytes 48 bytes Register Name: Register Description: Register Address: RIBOC Receive Interleave Bus Operation Control Register 088h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 IBOSEL 0 3 IBOEN 0 2 -- 0 1 -- 0 0 -- 0 Bit # Name Default 7 -- 0 Bit 4: Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode. 0 = Channel Interleave 1 = Frame Interleave Bit 3: Interleave Bus Operation Enable (IBOEN) 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. 162 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RSCC (T1 Mode Only) In-Band Receive Spare Control Register 089h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 RSC2 0 1 RSC1 0 0 RSC0 0 Bit # Name Default 7 -- 0 Bits 2 to 0: Receive Spare Code Length Definition Bits (RSC[2:0]) RSC2 0 0 0 0 1 1 1 1 RSC1 0 0 1 1 0 0 1 1 RSC0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 : 16 bits Register Name: Register Description: Register Address: RXPC Receive Expansion Port Control Register 08Ah + (200h x (n - 1)) : where n = 1 to 8 6 -- -- 0 5 -- -- 0 4 -- -- 0 3 -- -- 0 2 RBPDIR RBPDIR 0 1 RBPFUS -- 0 0 RBPEN RBPEN 0 Bit # Name Default 7 -- -- 0 Bit 2: Receive BERT Port Direction Control (RBPDIR) 0 = Normal (line) operation. Rx BERT port receives data from the receive framer. 1 = System (backplane) operation. Rx BERT port receives data from the transmit path. The transmit path enters the receive BERT on the line side of the elastic store (if enabled). Bit 1: Receive BERT Port Framed/Unframed Select (RBPFUS) (T1 Mode Only) 0 = The DS26518's receive BERT will not clock data from the F-bit position (framed). 1 = The DS26518's receive BERT will clock data from the F-bit position (unframed). Bit 0: Receive BERT Port Enable (RBPEN) 0 = Receive BERT port is not active. 1 = Receive BERT port is active. 163 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RBPBS Receive BERT Port Bit Suppress Register 08Bh + (200h x (n - 1)) : where n = 1 to 8 6 BPBSE7 0 5 BPBSE6 0 4 BPBSE5 0 3 BPBSE4 0 2 BPBSE3 0 1 BPBSE2 0 0 BPBSE1 0 Bit # Name Default 7 BPBSE8 0 Bit 7: Receive Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Receive Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used. Bit 5: Receive Channel Bit 6 Suppress (BPBSE6). Set to one to stop this bit from being used. Bit 4: Receive Channel Bit 5 Suppress (BPBSE5). Set to one to stop this bit from being used. Bit 3: Receive Channel Bit 4 Suppress (BPBSE4). Set to one to stop this bit from being used. Bit 2: Receive Channel Bit 3 Suppress (BPBSE3). Set to one to stop this bit from being used. Bit 1: Receive Channel Bit 2 Suppress (BPBSE2). Set to one to stop this bit from being used. Bit 0: Receive Channel Bit 1 Suppress (BPBSE1). LSB of the channel. Set to one to stop this bit from being used. 164 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS1 Receive Latched Status Register 1 090h + (200h x (n - 1)) : where n = 1 to 8 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RRAID 0 2 RAISD 0 1 RLOSD 0 0 RLOFD 0 Bit # Name Default 7 RRAIC 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC). Falling edge detect of RRAI. Set when a RRAI condition has cleared. Bit 6: Receive Alarm Indication Signal Condition Clear (RAISC). Falling edge detect of RAIS. Set when a RAIS condition has cleared. Bit 5: Receive Loss of Signal Condition Clear (RLOSC). Falling edge detect of RLOS. Set when an RLOS condition has cleared. Bit 4: Receive Loss of Frame Condition Clear (RLOFC). Falling edge detect of RLOF. Set when an RLOF condition has cleared. Bit 3: Receive Remote Alarm Indication Condition Detect (RRAID). Rising edge detect of RRAI. Set when a remote alarm is received at RRINGn and RTIPn. Bit 2: Receive Alarm Indication Signal Condition Detect (RAISD). Rising edge detect of RAIS.Set when an unframed all-ones code is received at RRINGn and RTIPn. Bit 1: Receive Loss of Signal Condition Detect (RLOSD). Rising edge detect of RLOS. Set when 192 consecutive zeros have been detected at RRINGn and RTIPn. Bit 0: Receive Loss of Frame Condition Detect (RLOFD). Rising edge detect of RLOF. Set when the DS26518 has lost synchronized to the received data stream. 165 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS2 (T1 Mode) Receive Latched Status Register 2 091h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 COFA 0 4 8ZD 0 3 16ZD 0 2 SEFE 0 1 B8ZS 0 0 FBE 0 Bit # Name Default 7 --0 Note: All bits in these register are latched. This register does not create interrupts. See RLS2 for E1 Mode. Bit 5: Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or multiframe alignment. Bit 4: Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at RRINGn and RTIPn. Bit 3: Sixteen Zero Detect Event (16ZD). Set when a string of at least sixteen consecutive zeros (regardless of the length of the string) have been received at RRINGn and RTIPn. Bit 2: Severely Errored Framing Event (SEFE). Set when 2 out of 6 framing bits (Ft or FPS) are received in error. Bit 1: B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RRINGn and RTIPn independent of whether the B8ZS mode is selected or not. Useful for automatically setting the line coding. Bit 0: Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error. Register Name: Register Description: Register Address: RLS2 (E1 Mode) E1 Receive Latched Status Register 2 091h + (200h x (n - 1)) : where n = 1 to 8 6 CRCRC 0 5 CASRC 0 4 FASRC 0 3 RSA1 0 2 RSA0 0 1 RCMF 0 0 RAF 0 Bit # Name Default 7 -- 0 Note: All bits in this register are latched. Bits 0 to 3 can cause interrupts. There is no associated real-time register. See RLS2 for T1 Mode. Bit 6: CRC Resync Criteria Met Event (CRCRC). Set when 915:1000 codewords are received in error. Bit 5: CAS Resync Criteria Met Event (CASRC). Set when 2 consecutive CAS MF alignment words are received in error. Bit 4: FAS Resync Criteria Met Event (FASRC). Set when 3 consecutive FAS words are received in error. Bit 3: Receive Signaling All Ones Event (RSA1). Set when the contents of time slot 16 contains fewer than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Bit 2: Receive Signaling All Zeros Event (RSA0). Set when over a full MF, time slot 16 contains all zeros. Bit 1: Receive CRC-4 Multiframe Event (RCMF). Set on CRC-4 multiframe boundaries; will continue to be set every 2ms on an arbitrary boundary if CRC-4 is disabled. Bit 0: Receive Align Frame Event (RAF). Set approximately every 250s to alert the host that Si and Sa bits are available in the RAF and RNAF registers. 166 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS3 (T1 Mode) Receive Latched Status Register 3 092h + (200h x (n - 1)) : where n = 1 to 8 6 LSPC 0 5 LDNC 0 4 LUPC 0 3 LORCD 0 2 LSPD 0 1 LDND 0 0 LUPD 0 Bit # Name Default 7 LORCC 0 Note: All bits in this register are latched and can create interrupts. See RLS3 for E1 Mode. Bit 7: Loss of Receive Clock Condition Clear (LORCC). Falling edge detect of LORC. Set when an LORC condition was detected and then removed. Bit 6: Spare Code Detected Condition Clear (LSPC). Falling edge detect of LSP. Set when a spare-code match condition was detected and then removed. Bit 5: Loop Down Code Detected Condition Clear (LDNC). Falling edge detect of LDN. Set when a loop-down condition was detected and then removed Bit 4: Loop Up Code Detected Condition Clear (LUPC). Falling edge detect of LUP. Set when a loop-up condition was detected and then removed. Bit 3: Loss of Receive Clock Condition Detect (LORCD). Rising edge detect of LORC. Set when the RCLKn pin has not transitioned for one channel time. Bit 2: Spare Code Detected Condition Detect (LSPD). Rising edge detect of LSP. Set when the spare code as defined in the T1RSCD1:T1RSCD2 registers is being received. Bit 1: Loop Down Code Detected Condition Detect (LDND). Rising edge detect of LDN. Set when the loop down code as defined in the T1RDNCD1:T1RDNCD2 register is being received. Bit 0: Loop Up Code Detected Condition Detect (LUPD). Rising edge detect of LUP. Set when the loop up code as defined in the T1RUPCD1:T1RUPCD2 register is being received. 167 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS3 (E1 Mode) Receive Latched Status Register 3 092h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 V52LNKC 0 4 RDMAC 0 3 LORCD 0 2 -- 0 1 V52LNKD 0 0 RDMAD 0 Bit # Name Default 7 LORCC 0 Note: All bits in this register are latched and can create interrupts. See RLS3 for T1 Mode. Bit 7: Loss of Receive Clock Clear (LORCC). Change of state indication. Set when an LORC condition has cleared (falling edge detect of LORC). Bit 5: V5.2 Link Detected Clear (V52LNKC). Change of state indication. Set when a V52LNK condition has cleared (falling edge detect of V52LNK). Bit 4: Receive Distant MF Alarm Clear (RDMAC). Change of state indication. Set when an RDMA condition has cleared (falling edge detect of RDMA). Bit 3: Loss of Receive Clock Detect (LORCD). Change of state indication. Set when the RCLKn pin has not transitioned for one channel time (rising edge detect of LORC). Bit 1: V5.2 Link Detect (V52LNKD). Change of state indication. Set on detection of a V5.2 link identification signal. (G.965). This is the rising edge detect of V52LNK. Bit 0: Receive Distant MF Alarm Detect (RDMAD). Change of state indication. Set when bit-6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This is the rising edge detect of RDMA. 168 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS4 Receive Latched Status Register 4 093h + (200h x (n - 1)) : where n = 1 to 8 6 RESEM 0 5 RSLIP 0 4 -- 0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0 Bit # Name Default 7 RESF 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is deleted. Bit 6: Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a frame is repeated. Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a frame. Bit 3: Receive Signaling Change Of State Event (RSCOS). Set when any channel selected by the Receive Signaling Change Of State Interrupt Enable registers (RSCSE1 through RSCSE3) changes signaling state. Bit 2: One-Second Timer (1SEC). Set on every one-second interval based on RCLKn. Bit 1: Timer Event (TIMER). This status bit indicates that the performance monitor counters have been updated and are available to be read by the host. The error counter update interval as determined by the settings in the Error Counter Configuration Register (ERCNT). T1: Set on increments of 1 second or 42ms based on RCLKn, or a manual latch event. E1: Set on increments of 1 second or 62.5ms based on RCLKn, or a manual latch event. Bit 0: Receive Multiframe Event (RMF) T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries. E1 Mode: Set every 2.0ms on receive CAS multiframe boundaries to alert host the signaling data is available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled. 169 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS5 Receive Latched Status Register 5 (HDLC) 094h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 2 RPS 0 1 RHWMS 0 0 RNES 0 Bit # Name Default 7 -- 0 Note: All bits in this register are latched and can cause interrupts. Bit 5: Receive FIFO Overrun (ROVR). Set when the receive HDLC controller has terminated packet reception because the FIFO buffer is full. Bit 4: Receive HDLC Opening Byte Event (RHOBT). Set when the next byte available in the receive FIFO is the first byte of a message. Bit 3: Receive Packet End Event (RPE). Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. This is a latched bit and will be cleared when read. Bit 2: Receive Packet Start Event (RPS). Set when the HDLC controller detects an opening byte. This is a latched bit and will be cleared when read. Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS). Set when the receive 64-byte FIFO crosses the high watermark as defined by the Receive HDLC FIFO Control Register (RHFC). Rising edge detect of RHWM. Bit 0: Receive FIFO Not Empty Set Event (RNES). Set when the receive FIFO has transitioned from "empty" to "not empty" (at least one byte has been put into the FIFO). Rising edge detect of RNE. 170 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS7 (T1 Mode) Receive Latched Status Register 7 096h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 RRAI-CI 0 4 RAIS-CI 0 3 RSLC96 0 2 RFDLF 0 1 BC 0 0 BD 0 Bit # Name Default 7 -- 0 Note: All bits in this register are latched and can create interrupts. See RLS7 for E1 Mode. Bit 5: Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver. This bit is active in ESF framing mode only, and will set only if an RAI condition is being detected (RRTS1.3). When the host reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1 seconds). Bit 4: Receive AIS-CI Detect (RAIS-CI). Set when an AIS-CI pattern has been detected by the receiver. This bit will set only if an AIS condition is being detected (RRTS1.2). This is a latched bit that must be cleared by the host, and will set again each time the AIS-CI pattern is detected (approximately every 1.2 seconds). Bit 3: Receive SLC-96 Alignment Event (RSLC96). Set when a valid SLC-96 alignment pattern is detected in the Fs bit stream, and the T1RSLC1-3 registers have data available for retrieval. See Section 9.9.4.4 for more information. Bit 2: Receive FDL Register Full Event (RFDLF). Set when the 8-bit T1RFDL register is full. Useful for SLC-96 operation, or manual extraction of FDL data bits. See Section 9.9.5.4 for more information. Bit 1: BOC Clear Event (BC). Set when a valid BOC is no longer detected (with the disintegration filter applied). Bit 0: BOC Detect Event (BD). Set when a valid BOC has been detected (with the BOC filter applied). Register Name: Register Description: Register Address: RLS7 (E1 Mode) Receive Latched Status Register 7 096h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 Sa6CD 0 0 SaXCD 0 Bit # Name Default 7 -- 0 Note: All bits in this register are latched and can create interrupts. See RLS7 for T1 Mode. Bit 1: Sa6 Codeword Detect (Sa6CD). Set when a valid codeword (per ETS 300 233) is detected in the Sa6 bit positions. Bit 0: SaX Bit Change Detect (SaXCD). Set when a bit change is detected in the SaX bit position. The enabled SaX bits are selected by theE1RSAIMR register. 171 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RSS1, RSS2, RSS3, RSS4 Receive-Signaling Status Registers 1 to 4 098h, 099h, 09Ah, 09Bh + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1* CH9 CH17* CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 RSS1 RSS2 RSS3 RSS4 (E1 Mode Only) Note: Status bits in this register are latched. When a channel's signaling data changes state, the respective bit in registers RSS1-4 will be set and latched. The RSCOS bit (RLS4.3) will be set if the channel was also enabled by setting the appropriate bit in RSCSE1-4. The INTB signal will go low if enabled by the interrupt mask bit RIM4.3. The bit will remain set until read. *Note that in E1 CAS mode, the LSB of RSS1 would typically represent the CAS alignment bits, and the LSB of RSS3 represents reserved bits and the distant multiframe alarm. 172 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RSCD1 (T1 Mode Only) Receive Spare Code Definition Register 1 09Ch + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Note: Writing this register resets the detector's integration period. Bit 7: Receive Spare Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Spare Code Definition Bit 6 (C6). A Don't Care if a 1-bit length is selected. Bit 5: Receive Spare Code Definition Bit 5 (C5). A Don't Care if a 1- or 2-bit length is selected. Bit 4: Receive Spare Code Definition Bit 4 (C4). A Don't Care if a 1- to 3-bit length is selected. Bit 3: Receive Spare Code Definition Bit 3 (C3). A Don't Care if a 1- to 4-bit length is selected. Bit 2: Receive Spare Code Definition Bit 2 (C2). A Don't Care if a 1- to 5-bit length is selected. Bit 1: Receive Spare Code Definition Bit 1 (C1). A Don't Care if a 1- to 6-bit length is selected. Bit 0: Receive Spare Code Definition Bit 0 (C0). A Don't Care if a 1- to 7-bit length is selected. Register Name: Register Description: Register Address: T1RSCD2 (T1 Mode Only) Receive Spare Code Definition Register 2 09Dh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Bit 7: Receive Spare Code Definition Bit 7 (C7). A Don't Care if a 1- to 7-bit length is selected. Bit 6: Receive Spare Code Definition Bit 6 (C6). A Don't Care if a 1- to 7-bit length is selected. Bit 5: Receive Spare Code Definition Bit 5 (C5). A Don't Care if a 1- to 7-bit length is selected. Bit 4: Receive Spare Code Definition Bit 4 (C4). A Don't Care if a 1- to 7-bit length is selected. Bit 3: Receive Spare Code Definition Bit 3 (C3). A Don't Care if a 1- to 7-bit length is selected. Bit 2: Receive Spare Code Definition Bit 2 (C2). A Don't Care if a 1- to 7-bit length is selected. Bit 1: Receive Spare Code Definition Bit 1 (C1). A Don't Care if a 1- to 7-bit length is selected. Bit 0: Receive Spare Code Definition Bit 0 (C0). A Don't Care if a 1- to 7-bit length is selected. 173 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIIR Receive Interrupt Information Register 9Fh + (200h x (n - 1)) : where n = 1 to 8 6 RLS7 0 5 RLS6* 0 4 RLS5 0 3 RLS4 0 2 RLS3 0 1 RLS2** 0 0 RLS1 0 Bit # Name Default 7 -- 0 * RLS6 is reserved for future use. ** Currently RLS2 does not create an interrupt, therefore this bit is not used in T1 mode. The Receive Interrupt Information Register indicates which of the DS26518 status registers are generating an interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the receive status registers is (are) causing the interrupt(s). The Receive Interrupt Information Register bits will clear once the appropriate interrupt has been serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated status register. Status bits that have been masked via the Receive Interrupt Mask (RIMx) registers will also be masked from the RIIR register. Register Name: Register Description: Register Address: RIM1 Receive Interrupt Mask Register 1 0A0h + (200h x (n - 1)) : where n = 1 to 8 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RRAID 0 2 RAISD 0 1 RLOSD 0 0 RLOFD 0 Bit # Name Default 7 RRAIC 0 Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Receive Alarm Indication Signal Condition Clear (RAISC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: Receive Loss of Signal Condition Clear (RLOSC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Receive Loss of Frame Condition Clear (RLOFC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3 : Receive Remote Alarm Indication Condition Detect (RRAID) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Receive Alarm Indication Signal Condition Detect (RAISD) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: Receive Loss of Signal Condition Detect (RLOSD) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Receive Loss of Frame Condition Detect (RLOFD) 0 = Interrupt masked. 1 = Interrupt enabled. 174 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIM2 (E1 Mode Only) E1 Receive Interrupt Mask Register 2 0A1h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 RSA1 0 2 RSA0 0 1 RCMF 0 0 RAF 0 Bit # Name Default 7 -- 0 Bit 3: Receive-Signaling All Ones Event (RSA1) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Receive-Signaling All Zeros Event (RSA0) 0 = Interrupt masked. 1 = interrupt enabled. Bit 1: Receive CRC-4 Multiframe Event (RCMF) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Receive Align Frame Event (RAF) 0 = Interrupt masked. 1 = Interrupt enabled. 175 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIM3 (T1 Mode) Receive Interrupt Mask Register 3 0A2h + (200h x (n - 1)) : where n = 1 to 8 6 LSPC 0 5 LDNC 0 4 LUPC 0 3 LORCD 0 2 LSPD 0 1 LDND 0 0 LUPD 0 Bit # Name Default 7 LORCC 0 Note: See RIM3 for E1 Mode. Bit 7: Loss of Receive Clock Condition Clear (LORCC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Spare Code Detected Condition Clear (LSPC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: Loop Down Code Detected Condition Clear (LDNC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Loop Up Code Detected Condition Clear (LUPC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Loss of Receive Clock Condition Detect (LORCD) 0 = Interrupt masked 1 = Interrupt enabled Bit 2: Spare Code Detected Condition Detect (LSPD) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1 : Loop Down Code Detected Condition Detect (LDND) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Loop Up Code Detected Condition Detect (LUPD) 0 = Interrupt masked. 1 = Interrupt enabled. 176 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIM3 (E1 Mode) E1 Receive Interrupt Mask Register 3 0A2h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 V52LNKC 0 4 RDMAC 0 3 LORCD 0 2 -- 0 1 V52LNKD 0 0 RDMAD 0 Bit # Name Default 7 LORCC 0 Note: See RIM3 for T1 Mode. Bit 7: Loss of Receive Clock Clear (LORCC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: V5.2 Link Detected Clear (V52LNKC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Receive Distant MF Alarm Clear (RDMAC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Loss of Receive Clock Detect (LORCD) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: V5.2 Link Detect (V52LNKD) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Receive Distant MF Alarm Detect (RDMAD) 0 = Interrupt masked. 1 = Interrupt enabled. 177 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIM4 Receive Interrupt Mask Register 4 0A3h + (200h x (n - 1)) : where n = 1 to 8 6 RESEM 0 5 RSLIP 0 4 -- 0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0 Bit # Name Default 7 RESF 0 Bit 7: Receive Elastic Store Full Event (RESF) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Receive Elastic Store Empty Event (RESEM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Receive Signaling Change Of State Event (RSCOS) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: One-Second Timer (1SEC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: Timer Event (TIMER) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Receive Multiframe Event (RMF) 0 = Interrupt masked. 1 = Interrupt enabled. 178 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIM5 Receive Interrupt Mask 5 (HDLC) 0A4h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 2 RPS 0 1 RHWMS 0 0 RNES 0 Bit # Name Default 7 -- 0 Bit 5: Receive FIFO Overrun (ROVR) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Receive HDLC Opening Byte Event (RHOBT) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Receive Packet End Event (RPE) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Receive Packet Start Event (RPS) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Receive FIFO Not Empty Set Event (RNES) 0 = Interrupt masked. 1 = Interrupt enabled. 179 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIM7 (T1 Mode) Receive Interrupt Mask Register 7 (BOC:FDL) 0A6h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 RRAI-CI 0 4 RAIS-CI 0 3 RSLC96 0 2 RFDLF 0 1 BC 0 0 BD 0 Bit # Name Default 7 -- 0 Note: See RIM7 for E1 Mode. Bit 5: Receive RAI-CI (RRAI-CI) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Receive AIS-CI (RAIS-CI) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Receive SLC-96 (RSLC96) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Receive FDL Register Full (RFDLF) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: BOC Clear Event (BC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: BOC Detect Event (BD) 0 = Interrupt masked. 1 = Interrupt enabled. Register Name: Register Description: Register Address: RIM7 (E1 Mode) Receive Interrupt Mask Register 7 (BOC:FDL) 0A6h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 Sa6CD 0 0 SaXCD 0 Bit # Name Default 7 -- 0 Note: See RIM7 for T1 Mode. Bit 1: Sa6 Codeword Detect (Sa6CD). This bit will enable the interrupt generated when a valid codeword (per ETS 300 233) is detected in the Sa6 bits. 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: SaX Change Detect (SaXCD). This bit will enable the interrupt generated when a change of state is detected in any of the unmasked SaX bit positions. The masked or unmasked SaX bits are selected by the E1RSAIMR register. 0 = Interrupt masked. 1 = Interrupt enabled. 180 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Receive-Signaling Change of State Enable Registers 1 to 4 0A8h, 0A9h, 0AAh, 0ABh + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 RSCSE1 RSCSE2 RSCSE3 RSCSE4 (E1 Mode Only) Setting any of the CH[1:32] bits in the RSCSE1 to RSCSE4 registers will cause RSCOS (RLS4.3) to be set when that channel's signaling data changes state. 181 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RUPCD1 (T1 Mode Only) Receive Up Code Definition Register 1 0ACh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Note: Writing this register resets the detector's integration period. Bit 7: Receive Up Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Up Code Definition Bit 6 (C6). A Don't Care if a 1-bit length is selected. Bit 5: Receive Up Code Definition Bit 5 (C5). A Don't Care if a 1- or 2-bit length is selected. Bit 4: Receive Up Code Definition Bit 4 (C4). A Don't Care if a 1- to 3-bit length is selected. Bit 3: Receive Up Code Definition Bit 3 (C3). A Don't Care if a 1- to 4-bit length is selected. Bit 2: Receive Up Code Definition Bit 2 (C2). A Don't Care if a 1- to 5-bit length is selected. Bit 1: Receive Up Code Definition Bit 1 (C1). A Don't Care if a 1- to 6-bit length is selected. Bit 0: Receive Up Code Definition Bit 0 (C0). A Don't Care if a 1- to 7-bit length is selected. Register Name: Register Description: Register Address: T1RUPCD2 (T1 Mode Only) Receive Up Code Definition Register 2 0ADh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Bit 7: Receive Up Code Definition Bit 7 (C7). A Don't Care if a 1- to 7-bit length is selected. Bit 6: Receive Up Code Definition Bit 6 (C6). A Don't Care if a 1- to 7-bit length is selected. Bit 5: Receive Up Code Definition Bit 5 (C5). A Don't Care if a 1- to 7-bit length is selected. Bit 4: Receive Up Code Definition Bit 4 (C4). A Don't Care if a 1- to 7-bit length is selected. Bit 3: Receive Up Code Definition Bit 3 (C3). A Don't Care if a 1- to 7-bit length is selected. Bit 2: Receive Up Code Definition Bit 2 (C2). A Don't Care if a 1- to 7-bit length is selected. Bit 1: Receive Up Code Definition Bit 1 (C1). A Don't Care if a 1- to 7-bit length is selected. Bit 0: Receive Up Code Definition Bit 0 (C0). A Don't Care if a 1- to 7-bit length is selected. 182 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RDNCD1 (T1 Mode Only) Receive Down Code Definition Register 1 0AEh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Note: Writing this register resets the detector's integration period. Bit 7: Receive Down Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Down Code Definition Bit 6 (C6). A Don't Care if a 1-bit length is selected. Bit 5: Receive Down Code Definition Bit 5 (C5). A Don't Care if a 1- or 2-bit length is selected. Bit 4: Receive Down Code Definition Bit 4 (C4). A Don't Care if a 1- to 3-bit length is selected. Bit 3: Receive Down Code Definition Bit 3 (C3). A Don't Care if a 1- to 4-bit length is selected. Bit 2: Receive Down Code Definition Bit 2 (C2). A Don't Care if a 1- to 5-bit length is selected. Bit 1: Receive Down Code Definition Bit 1 (C1). A Don't Care if a 1- to 6-bit length is selected. Bit 0: Receive Down Code Definition Bit 0 (C0). A Don't Care if a 1- to 7-bit length is selected. Register Name: Register Description: Register Address: T1RDNCD2 (T1 Mode Only) Receive Down Code Definition Register 2 0AFh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Bit 7: Receive Down Code Definition Bit 7 (C7). A Don't Care if a 1- to 7-bit length is selected. Bit 6: Receive Down Code Definition Bit 6 (C6). A Don't Care if a 1- to 7-bit length is selected. Bit 5: Receive Down Code Definition Bit 5 (C5). A Don't Care if a 1- to 7-bit length is selected. Bit 4: Receive Down Code Definition Bit 4 (C4). A Don't Care if a 1- to 7-bit length is selected. Bit 3: Receive Down Code Definition Bit 3 (C3). A Don't Care if a 1- to 7-bit length is selected. Bit 2: Receive Down Code Definition Bit 2 (C2). A Don't Care if a 1- to 7-bit length is selected. Bit 1: Receive Down Code Definition Bit 1 (C1). A Don't Care if a 1- to 7-bit length is selected. Bit 0: Receive Down Code Definition Bit 0 (C0). A Don't Care if a 1- to 7-bit length is selected. 183 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RRTS1 Receive Real-Time Status Register 1 0B0h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 RRAI 0 2 RAIS 0 1 RLOS 0 0 RLOF 0 Bit # Name Default 7 -- 0 Note: All bits in this register are real-time (not latched). Bit 3: Receive Remote Alarm Indication Condition (RRAI). Set when a remote alarm is received at RRINGn and RTIPn. Bit 2: Receive Alarm Indication Signal Condition (RAIS). Set when an unframed all-ones code is received at RRINGn and RTIPn. Bit 1: Receive Loss of Signal Condition (RLOS). Set when 192 consecutive zeros have been detected at RRINGn and RTIPn. Bit 0: Receive Loss of Frame Condition (RLOF). Set when the DS26518 is not synchronized to the received data stream. 184 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RRTS3 (T1 Mode) Receive Real-Time Status Register 3 0B2h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 LORC 0 2 LSP 0 1 LDN 0 0 LUP 0 Bit # Name Default 7 -- 0 Note: All bits in this register are real-time (not latched). See RRTS3 for E1 Mode. Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLKn pin has not transitioned for one channel time. Bit 2: Spare Code Detected Condition (LSP). Set when the spare code as defined in the T1RSCD1:T1RSCD2 registers is being received. Bit 1: Loop-Down Code Detected Condition (LDN). Set when the loop-down code as defined in the T1RDNCD1:T1RDNCD2 register is being received. Bit 0: Loop-Up Code Detected Condition (LUP). Set when the loop-up code as defined in the T1RUPCD1:T1RUPCD2 register is being received. Register Name: Register Description: Register Address: RRTS3 (E1 Mode) Receive Real-Time Status Register 3 0B2h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 LORC 0 2 -- 0 1 V52LNK 0 0 RDMA 0 Bit # Name Default 7 -- 0 Note: All bits in this register are real-time (not latched). See RRTS3 for T1 Mode. Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLKn pin has not transitioned for one channel time. Bit 1: V5.2 Link Detected Condition (V52LNK). Set on detection of a V5.2 link identification signal (G.965). Bit 0: Receive Distant MF Alarm Condition (RDMA). Set when bit-6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. 185 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RRTS5 Receive Real-Time Status Register 5 (HDLC) 0B4h + (200h x (n - 1)) : where n = 1 to 8 6 PS2 0 5 PS1 0 4 PS0 0 3 -- 0 2 -- 0 1 RHWM 0 0 RNE 0 Bit # Name Default 7 -- 0 Note: All bits in this register are real time. Bits 6 to 4: Receive Packet Status (PS[2:0]). These are real-time bits indicating the status as of the last read of the receive FIFO. PS2 0 0 0 0 1 PS1 0 0 1 1 0 PS0 0 1 0 1 0 PACKET STATUS In Progress: End of message has not yet been reached. Packet OK: Packet ended with correct CRC codeword. CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword. Abort: Packet ended because an abort signal was detected (7 or more ones in a row). Overrun: HDLC controller terminated reception of packet because receive FIFO is full. Bit 1: Receive FIFO Above High Watermark Condition (RHWM). Set when the receive 64-byte FIFO fills beyond the high watermark as defined by the Receive HDLC FIFO Control Register (RHFC). This is a real-time bit. Bit 0: Receive FIFO Not Empty Condition (RNE). Set when the receive 64-byte FIFO has at least one byte available for a read. This is a real-time bit. Register Name: Register Description: Register Address: RHPBA Receive HDLC Packet Bytes Available Register 0B5h + (200h x (n - 1)) : where n = 1 to 8 6 RPBA6 0 5 RPBA5 0 4 RPBA4 0 3 RPBA3 0 2 RPBA2 0 1 RPBA1 0 0 RPBA0 0 Bit # Name Default 7 MS 0 Bit 7: Message Status (MS) 0 = Bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the HDLC Status register for details. 1 = Bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not need to check the HDLC Status. The MS bit will return to a value of `1' when the Rx HDLC FIFO is empty. Bits 6 to 0: Receive FIFO Packet Bytes Available Count (RPBA[6:0]). RPBA0 is the LSB. 186 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RHF Receive HDLC FIFO Register 0B6h + (200h x (n - 1)) : where n = 1 to 8 6 RHD6 0 5 RHD5 0 4 RHD4 0 3 RHD3 0 2 RHD2 0 1 RHD1 0 0 RHD0 0 Bit # Name Default 7 RHD7 0 Bit 7: Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte. Bit 6: Receive HDLC Data Bit 6 (RHD6) Bit 5: Receive HDLC Data Bit 5 (RHD5) Bit 4: Receive HDLC Data Bit 4 (RHD4) Bit 3: Receive HDLC Data Bit 3 (RHD3) Bit 2: Receive HDLC Data Bit 2 (RHD2) Bit 1: Receive HDLC Data Bit 1 (RHD1) Bit 0: Receive HDLC Data Bit 0 (RHD0). LSB of a HDLC packet data byte. Register Name: Register Description: Register Address: RBCS1, RBCS2, RBCS3, RBCS4 Receive Blank Channel Select Registers 1 to 4 0C0h, 0C1h, 0C2h, 0C3h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 RBCS1 RBCS2 RBCS3 RBCS4 (E1 Mode Only) Bits 7 to 0: Receive Blank Channel Select for Channels 1 to 32 (CH[1:32]) 0 = Do not blank this channel (channel data is available on RSERn). 1 = Data on RSERn is forced to all ones for this channel. Note that when two or more sequential channels are chosen to be blanked, the receive-slip zone select bit should be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), then the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications. 187 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RCBR1, RCBR2, RCBR3, RCBR4 Receive Channel Blocking Registers 1 to 4 0C4h, 0C5h, 0C6h, 0C7h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 (LSB) 0 CH1 CH9 CH17 CH25 (F-bit) RCBR1 RCBR2 RCBR3 RCBR4 (E1 Mode Only)* Bits 7 to 0: Channel Blocking Control Bits for Receive Channels 1 to 32 (CH[1:32]) 0 = Force the RCHBLKn pin to remain low during this channel time. 1 = Force the RCHBLKn pin high during this channel time. *Note that RCBR4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking signal for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the RCHBLKn signal will pulse high during the F-bit time. In this mode RCBR4.1 to RCBR4.7 should be set to 0. RCBR4.0 = 0, do not pulse RCHBLKn during the F-bit. RCBR4.0 = 1, pulse RCHBLKn during the F-bit. Register Name: Register Description: Register Address: RSI1, RSI2, RSI3, RSI4 Receive-Signaling Reinsertion Enable Registers 1 to 4 0C8h, 0C9h, 0CAh, 0CBh + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 RSI1 RSI2 RSI3 RSI4 (E1 Mode Only) Setting any of the CH[1:24] bits in the RSI1 through RSI4 registers will cause signaling data to be reinserted for the associated channel. RSI4 is used for 2.048MHz backplane operation. 188 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RGCCS1, RGCCS2, RGCCS3, RGCCS4 Receive Gapped Clock Channel Select Registers 1 to 4 0CCh, 0CDh, 0CEh, 0CFh + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 (F-bit) Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 RGCCS1 RGCCS2 RGCCS3 RGCCS4 (E1 Mode Only)* Bits 7 to 0: Gapped Clock Channel Select Bits for Receive Channels 1 to 32(CH[1:32]) 0 = No clock is present on RCHCLKn during this channel time. 1 = Force a clock on RCHCLKn during this channel time. The clock will be synchronous with RCLKn if the elastic store is disabled, and synchronous with RSYSCLKn if the elastic store is enabled. * Note that RGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on RCHCLKn for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on RCHCLKn during the F-bit time: RGCCS4.0 = 0, do not generate a clock during the F-bit. RGCCS4.0 = 1, generate a clock during the F-bit. In this mode RGCCS4.1 to RGCCS4.7 should be set to 0. Register Name: Register Description: Register Address: RCICE1, RCICE2, RCICE3, RCICE4 Receive Channel Idle Code Enable Registers 1 to 4 0D0h, 0D1h, 0D2h, 0D3h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 RCICE1 RCICE2 RCICE3 RCICE4 (E1 Mode Only) Bits 7 to 0: Receive Channels 1 to 32 Code Insertion Control Bits (CH[1:32]) 0 = Do not insert data from the Idle Code Array into the receive data stream. 1 = Insert data from the Idle Code Array into the receive data stream. 189 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RBPCS1, RBPCS2, RBPCS3, RBPCS4 Receive BERT Port Channel Select Registers 1 to 4 0D4h, 0D5h, 0D6h, 0D7h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 RBPCS1 RBPCS2 RBPCS3 RBPCS4 (E1 Mode Only) Bits 7 to 0: BERT Port Channel Select Receive Channels 1 to 32 (CH[1:32]) 0 = Do not enable the receive BERT clock for the associated channel time, or map the selected channel data out of the receive BERT port. 1 = Enable receive BERT clock for the associated channel time, and allow mapping of the selected channel data out of the receive BERT port. Multiple or all channels may be selected simultaneously. 190 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.4.2 Transmit Register Descriptions Register Name: Register Description: Register Address: THC1 Transmit HDLC Control Register 1 110h + (200h x (n - 1)) : where n = 1 to 8 6 TEOML 0 5 THR 0 4 THMS 0 3 TFS 0 2 TEOM 0 1 TZSD 0 0 TCRCD 0 Bit # Name Default 7 NOFS 0 Bit 7: Number Of Flags Select (NOFS) 0 = Send one flag between consecutive messages. 1 = Send two flags between consecutive messages. Bit 6: Transmit End of Message and Loop (TEOML). To loop on a message, should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the user clears this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message will complete then flags will be transmitted until new message is written to the FIFO. If the host terminates the loop by writing a new message to the FIFO the loop will terminate, one or two flags will be transmitted and the new message will start. If not disabled via TCRCD, the transmitter will automatically append a two-byte CRC code to the end of all messages. Bit 5: Transmit HDLC Reset (THR). Will reset the transmit HDLC controller and flush the transmit FIFO. An abort followed by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the FIFO. This is an acknowledged reset, that is, the host need only to set the bit and the DS26518 will clear it once the reset operation is complete. Total time for the reset is less than 250s. 0 = Normal operation. 1 = Reset transmit HDLC controller and flush the transmit FIFO. Bit 4: Transmit HDLC Mapping Select (THMS) 0 = Transmit HDLC assigned to channels. 1 = Transmit HDLC assigned to FDL (T1 mode), Sa bits (E1 mode). This mode must be enabled with T1.TCR2.7. Bit 3: Transmit Flag/Idle Select (TFS). This bit selects the inter-message fill character after the closing and before the opening flags (7Eh). 0 = 7Eh 1 = FFh Bit 2: Transmit End of Message (TEOM). Should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO at THF. If not disabled via TCRCD, the transmitter will automatically append a two byte CRC code to the end of the message. Bit 1: Transmit Zero Stuffer Defeat (TZSD). The zero stuffer function automatically inserts a zero in the message field (between the flags) after five consecutive ones to prevent the emulation of a flag or abort sequence by the data pattern. The receiver automatically removes (de-stuffs) any zero after five ones in the message field. 0 = Enable the zero stuffer (normal operation). 1 = Disable the zero stuffer. Bit 0: Transmit CRC Defeat (TCRCD). A two-byte CRC code is automatically appended to the outbound message. This bit can be used to disable the CRC function. 0 = Enable CRC generation (normal operation). 1 = Disable CRC generation. 191 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: THBSE Transmit HDLC Bit Suppress 111h + (200h x (n - 1)) : where n = 1 to 8 6 TBSE7 0 5 TBSE6 0 4 TBSE5 0 3 TBSE4 0 2 TBSE3 0 1 TBSE2 0 0 TBSE1 0 Bit # Name Default 7 TBSE8 0 Bit 7: Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Transmit Bit 7 Suppress (TBSE7). Set to one to stop this bit from being used. Bit 5: Transmit Bit 6 Suppress (TBSE6). Set to one to stop this bit from being used. Bit 4: Transmit Bit 5 Suppress (TBSE5). Set to one to stop this bit from being used. Bit 3: Transmit Bit 4 Suppress (TBSE4). Set to one to stop this bit from being used. Bit 2: Transmit Bit 3 Suppress (TBSE3). Set to one to stop this bit from being used. Bit 1: Transmit Bit 2 Suppress (TBSE2). Set to one to stop this bit from being used. Bit 0: Transmit Bit 1 Suppress (TBSE1). LSB of the channel. Set to one to stop this bit from being used. Register Name: Register Description: Register Address: THC2 Transmit HDLC Control Register 2 113h + (200h x (n - 1)) : where n = 1 to 8 6 SBOC -- 0 5 THCEN THCEN 0 4 THCS4 THCS4 0 3 THCS3 THCS3 0 2 THCS2 THCS2 0 1 THCS1 THCS1 0 0 THCS0 THCS0 0 Bit # Name Default 7 TABT TABT 0 Bit 7: Transmit Abort (TABT). A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Bit 6: Send BOC (SBOC) (T1 Mode Only). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the T1TBOC register. Bit 5: Transmit HDLC Controller Enable (THCEN) 0 = Transmit HDLC Controller is not enabled 1 = Transmit HDLC Controller is enabled Bits 4 to 0: Transmit HDLC Channel Select (THCS[4:0]). Determines which DSO channel will carry the HDLC message if enabled. Changes to this value are acknowledged only upon a transmit HDLC controller reset (THR at THC1.5). 192 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1TSACR E1 Transmit Sa-Bit Control Register 114h + (200h x (n - 1)) : where n = 1 to 8, for Ports 1 to 8 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit # Name Default 7 SiAF 0 Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF) 0 = Do not insert data from the E1TSiAF register into the transmit data stream. 1 = Insert data from the E1TSiAF register into the transmit data stream. Bit 6: International Bit in Non-Align Frame Insertion Control Bit (SiNAF) 0 = Do not insert data from the E1TSiNAF register into the transmit data stream. 1 = Insert data from the E1TSiNAF register into the transmit data stream. Bit 5: Remote Alarm Insertion Control Bit (RA) 0 = Do not insert data from the E1TRA register into the transmit data stream. 1 = Insert data from the E1TRA register into the transmit data stream. Bit 4: Additional Bit 4 Insertion Control Bit (Sa4) 0 = Do not insert data from the E1TSa4 register into the transmit data stream. 1 = Insert data from the E1TSa4 register into the transmit data stream. Bit 3: Additional Bit 5 Insertion Control Bit (Sa5) 0 = Do not insert data from the E1TSa5 register into the transmit data stream. 1 = Insert data from the E1TSa5 register into the transmit data stream. Bit 2: Additional Bit 6 Insertion Control Bit (Sa6) 0 = Do not insert data from the E1TSa6 register into the transmit data stream. 1 = Insert data from the E1TSa6 register into the transmit data stream. Bit 1: Additional Bit 7 Insertion Control Bit (Sa7) 0 = Do not insert data from the E1TSa7 register into the transmit data stream. 1 = Insert data from the E1TSa7 register into the transmit data stream. Bit 0: Additional Bit 8 Insertion Control Bit (Sa8) 0 = Do not insert data from the E1TSa8 register into the transmit data stream. 1 = Insert data from the E1TSa8 register into the transmit data stream. 193 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: (MSB) 7 CH8 CH16 CH24 CH32 SSIE1, SSIE2, SSIE3, SSIE4 Software-Signaling Insertion Enable Registers 1 to 4 118h, 119h, 11Ah, 11Bh + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 SSIE1 SSIE2 SSIE3 SSIE4 (E1 Mode Only) Bits 7 to 0: Software-Signaling Insertion Enable for Channels 1 to 32 (CH[1:32]). These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = Do not source signaling data from the TS registers for this channel. 1 = Source signaling data from the TS registers for this channel. Register Name: Register Description: Register Address: TIDR1 to TIDR32 Transmit Idle Code Definition Registers 1 to 32 120h to 13Fh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the code (this bit is transmitted last). Address 120h is for channel 1, address 13Fh is for channel 32. TIDR25:TIDR32 are E1 mode. 194 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TS1 to TS16 Transmit-Signaling Registers 140h to 14Fh + (200h x (n - 1)) : where n = 1 to 8 T1 Mode: Bit # Name (MSB) 7 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A 6 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B 5 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C 4 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D 3 CH13-A CH14-A CH15-A CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A 2 CH13-B CH14-B CH15-B CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B 1 CH13-C CH14-C CH15-C CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C (LSB) 0 CH13-D CH14-D CH15-D CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 Note: In D4 framing mode, the C and D bits are not used. E1 Mode: Bit # Name (MSB) 7 0 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A CH13-A CH14-A CH15-A 6 0 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B CH13-B CH14-B CH15-B 5 0 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH13-C CH14-C CH15-C 4 0 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-D CH14-D CH15-D 3 X CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH25-A CH26-A CH27-A CH28-A CH29-A CH30-A 2 Y CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH25-B CH26-B CH27-B CH28-B CH29-B CH30-B 1 X CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C CH25-C CH26-C CH27-C CH28-C CH29-C CH30-C (LSB) 0 X CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH25-D CH26-D CH27-D CH28-D CH29-D CH30-D TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 195 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TCICE1, TCICE2, TCICE3, TCICE4 Transmit Channel Idle Code Enable Registers 1 to 4 150h, 151h, 152h, 153h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 TCICE1 TCICE2 TCICE3 TCICE4 (E1 Mode Only) The Transmit Channel Idle Code Enable Registers (TCICE1-4) are used to determine which of the 24 T1 channels (or 32 E1 channels) from the backplane should be overwritten with the code placed in the Transmit Idle Code Definition Register (TIDR1-32). Bits 7 to 0: Transmit Channels 1 to 32 Code Insertion Control Bits (CH[1:32]) 0 = Do not insert data from the Idle Code Array into the transmit data stream. 1 = Insert data from the Idle Code Array into the transmit data stream. Register Name: Register Description: Register Address: TJBE1, TJBE2, TJBE3, TJBE4 Transmit Jammed Bit Eight Stuffing Registers 1 to 4 104h, 105h, 106h, 107h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 TJBE1 TJBE2 TJBE3 TJBE4 The Transmit Jammed Bit Eight Stuffing Registers (TJBE1-4) select which of the 24 T1 channels (or 32 E1 Channels) to insert jammed bit eight stuffing. These registers are enabled by TCR4.TJBEN. Bits 7 to 0: Transmit Channels 1 to 32 Jammed Bit Eight Stuffing Control Bits (CH[1:32]) 0 = Do not affect data in this channel. 1 = Replace the channel with TJBES if the channel is all zeros. 196 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TDDS1, TDDS2, TDDS3 Transmit DDS Zero Code Registers 1 to 3 108h, 109h, 10Ah + (200h x (n - 1)) : where n = 1 to 8 (LSB) CH1 CH9 CH17 (MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 TDDS1 TDDS2 TDDS3 The Transmit DDS Zero Code Registers (TDDS1-3) select which of the 24 T1 channels to insert DDS zero code stuffing. These registers are enabled by T1.TCR2.TDDSEN. Bits 7 to 0: Transmit Channels 1 to 24 DDS Zero Code Control Bits (CH[1:32]) 0 = Do not affect data in this channel. 1 = Replace the channel with DDS Zero Code stuffing if the channel is all zeros. Register Name: Register Description: Register Address: TFRID Transmit Firmware Revision ID Register 161h + (200h x (n - 1)) : where n = 1 to 8 6 FR6 0 5 FR5 0 4 FR4 0 3 FR3 0 2 FR2 0 1 FR1 0 0 FR0 0 Bit # Name Default 7 FR7 0 Bits 7 to 0: Firmware Revision (FR[7:0]). This read-only register reports the transmitter firmware revision. Register Name: Register Description: Register Address: T1TFDL Transmit FDL Register 162h + (200h x (n - 1)) : where n = 1 to 8 6 TFDL6 0 5 TFDL5 0 4 TFDL4 0 3 TFDL3 0 2 TFDL2 0 1 TFDL1 0 0 TFDL0 0 Bit # Name Default 7 TFDL7 0 Note: Also used to insert Fs framing pattern in D4 framing mode. The Transmit FDL Register (T1TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used. Bit 7: Transmit FDL Bit 7 (TFDL7). MSB of the Transmit FDL Code. Bit 6: Transmit FDL Bit 6 (TFDL6) Bit 5: Transmit FDL Bit 5 (TFDL5) Bit 4: Transmit FDL Bit 4 (TFDL4) Bit 3: Transmit FDL Bit 3 (TFDL3) Bit 2: Transmit FDL Bit 2 (TFDL2) Bit 1: Transmit FDL Bit 1 (TFDL1) Bit 0: Transmit FDL Bit 0 (TFDL0). LSB of the Transmit FDL Code. 197 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1TBOC Transmit BOC Register 163h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 TBOC5 0 4 TBOC4 0 3 TBOC3 0 2 TBOC2 0 1 TBOC1 0 0 TBOC0 0 Bit # Name Default 7 -- 0 Bit 5: Transmit BOC Bit 5 (TBOC5). MSB of the transmit BOC code. Bit 4: Transmit BOC Bit 4 (TBOC4) Bit 3: Transmit BOC Bit 3 (TBOC3) Bit 2: Transmit BOC Bit 2 (TBOC2) Bit 1: Transmit BOC Bit 1 (TBOC1) Bit 0: Transmit BOC Bit 0 (TBOC0). LSB of the transmit BOC code. 198 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1TSLC1, T1TSLC2, T1TSLC3 (T1 Mode) Transmit SLC-96 Data Link Registers 1 to 3 164h, 165h, 166h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 C1 C9 M3 Bit # Name (MSB) 7 C8 M2 S=1 6 C7 M1 S4 5 C6 S=0 S3 4 C5 S=1 S2 3 C4 S=0 S1 2 C3 C11 A2 1 C2 C10 A1 T1TSLC1 T1TSLC2 T1TSLC3 Note: See E1TAF, E1TNAF, and E1TSiAF for E1 Mode. Register Name: Register Description: Register Address: E1TAF (E1 Mode) Transmit Align Frame Register 164h + (200h x (n - 1)) : where n = 1 to 8 6 0 0 5 0 0 4 1 1 3 1 1 2 0 0 1 1 1 0 1 1 Bit # Name Default 7 Si 0 Bit 7: International Bit (Si) Bit 6: Frame Alignment Signal Bit (0) Bit 5: Frame Alignment Signal Bit (0) Bit 4: Frame Alignment Signal Bit (1) Bit 3: Frame Alignment Signal Bit (1) Bit 2: Frame Alignment Signal Bit (0) Bit 1: Frame Alignment Signal Bit (1) Bit 0: Frame Alignment Signal Bit (1) Register Name: Register Description: Register Address: E1TNAF (E1 Mode) Transmit Non-Align Frame Register 165h + (200h x (n - 1)) : where n = 1 to 8 6 1 1 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit # Name Default 7 Si 0 Bit 7: International Bit (Si) Bit 6: Frame Non-Alignment Signal Bit (1) Bit 5: Remote Alarm (Used to Transmit the Alarm) (A) Bit 4: Additional Bit 4 (Sa4) Bit 3: Additional Bit 5 (Sa5) Bit 2: Additional Bit 6 (Sa6) Bit 1: Additional Bit 7 (Sa7) Bit 0: Additional Bit 8 (Sa8) 199 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1TSiAF (E1 Mode) Transmit Si Bits of the Align Frame Register 166h + (200h x (n - 1)) : where n = 1 to 8 6 TSiF12 0 5 TSiF10 0 4 TSiF8 0 3 TSiF6 0 2 TSiF4 0 1 TSiF2 0 0 TSiF0 0 Bit # Name Default 7 TSiF14 0 Bit 7: Si Bit of Frame 14 (TSiF14) Bit 6: Si Bit of Frame 12 (TSiF12) Bit 5: Si Bit of Frame 10 (TSiF10) Bit 4: Si Bit of Frame 8 (TSiF8) Bit 3: Si Bit of Frame 6 (TSiF6) Bit 2: Si Bit of Frame 4 (TSiF4) Bit 1: Si Bit of Frame 2 (TSiF2) Bit 0: Si Bit of Frame 0 (TSiF0) Register Name: Register Description: Register Address: E1TSiNAF (E1 Mode Only) Transmit Si Bits of the Non-Align Frame Register 167h + (200h x (n - 1)) : where n = 1 to 8 6 TSiF13 0 5 TSiF11 0 4 TSiF9 0 3 TSiF7 0 2 TSiF5 0 1 TSiF3 0 0 TSiF1 0 Bit # Name Default 7 TSiF15 0 Bit 7: Si Bit of Frame 15 (TSiF15) Bit 6: Si Bit of Frame 13 (TSiF13) Bit 5: Si Bit of Frame 11 (TSiF11) Bit 4: Si Bit of Frame 9 (TSiF9) Bit 3: Si Bit of Frame 7 (TSiF7) Bit 2: Si Bit of Frame 5 (TSiF5) Bit 1: Si Bit of Frame 3 (TSiF3) Bit 0: Si Bit of Frame 1 (TSiF1) 200 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1TRA (E1 Mode Only) Transmit Remote Alarm Register 168h + (200h x (n - 1)) : where n = 1 to 8 6 TRAF13 0 5 TRAF11 0 4 TRAF9 0 3 TRAF7 0 2 TRAF5 0 1 TRAF3 0 0 TRAF1 0 Bit # Name Default 7 TRAF15 0 Bit 7: Remote Alarm Bit of Frame 15 (TRAF15) Bit 6: Remote Alarm Bit of Frame 13 (TRAF13) Bit 5: Remote Alarm Bit of Frame 11 (TRAF11) Bit 4: Remote Alarm Bit of Frame 9 (TRAF9) Bit 3: Remote Alarm Bit of Frame 7 (TRAF7) Bit 2: Remote Alarm Bit of Frame 5 (TRAF5) Bit 1: Remote Alarm Bit of Frame 3 (TRAF3) Bit 0: Remote Alarm Bit of Frame 1 (TRAF1) Register Name: Register Description: Register Address: E1TSa4 (E1 Mode Only) Transmit Sa4 Bits Register 169h + (200h x (n - 1)) : where n = 1 to 8 6 TSa4F13 0 5 TSa4F11 0 4 TSa4F9 0 3 TSa4F7 0 2 TSa4F5 0 1 TSa4F3 0 0 TSa4F1 0 Bit # Name Default 7 TSa4F15 0 Bit 7: Sa4 Bit of Frame 15 (TSa4F15) Bit 6: Sa4 Bit of Frame 13 (TSa4F13) Bit 5: Sa4 Bit of Frame 11 (TSa4F11) Bit 4: Sa4 Bit of Frame 9 (TSa4F9) Bit 3: Sa4 Bit of Frame 7 (TSa4F7) Bit 2: Sa4 Bit of Frame 5 (TSa4F5) Bit 1: Sa4 Bit of Frame 3 (TSa4F3) Bit 0: Sa4 Bit of Frame 1 (TSa4F1) 201 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1TSa5 (E1 Mode Only) Transmit Sa5 Bits Register 16Ah + (200h x (n - 1)) : where n = 1 to 8 6 TSa5F13 0 5 TSa5F11 0 4 TSa5F9 0 3 TSa5F7 0 2 TSa5F5 0 1 TSa5F3 0 0 TSa5F1 0 Bit # Name Default 7 TSa5F15 0 Bit 7: Sa5 Bit of Frame 15 (TSa5F15) Bit 6: Sa5 Bit of Frame 13 (TSa5F13) Bit 5: Sa5 Bit of Frame 11 (TSa5F11) Bit 4: Sa5 Bit of Frame 9 (TSa5F9) Bit 3: Sa5 Bit of Frame 7 (TSa5F7) Bit 2: Sa5 Bit of Frame 5 (TSa5F5) Bit 1: Sa5 Bit of Frame 3 (TSa5F3) Bit 0: Sa5 Bit of Frame 1 (TSa5F1) Register Name: Register Description: Register Address: E1TSa6 (E1 Mode Only) Transmit Sa6 Bits Register 16Bh + (200h x (n - 1)) : where n = 1 to 8 6 TSa6F13 0 5 TSa6F11 0 4 TSa6F9 0 3 TSa6F7 0 2 TSa6F5 0 1 TSa6F3 0 0 TSa6F1 0 Bit # Name Default 7 TSa6F15 0 Bit 7: Sa6 Bit of Frame 15 (TSa6F15) Bit 6: Sa6 Bit of Frame 13 (TSa6F13) Bit 5: Sa6 Bit of Frame 11 (TSa6F11) Bit 4: Sa6 Bit of Frame 9 (TSa6F9) Bit 3: Sa6 Bit of Frame 7 (TSa6F7) Bit 2: Sa6 Bit of Frame 5 (TSa6F5) Bit 1: Sa6 Bit of Frame 3 (TSa6F3) Bit 0: Sa6 Bit of Frame 1 (TSa6F1) 202 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1TSa7 (E1 Mode Only) Transmit Sa7 Bits Register 16Ch + (200h x (n - 1)) : where n = 1 to 8 6 TSa7F13 0 5 TSa7F11 0 4 TSa7F9 0 3 TSa7F7 0 2 TSa7F5 0 1 TSa7F3 0 0 TSa7F1 0 Bit # Name Default 7 TSa7F15 0 Bit 7: Sa7 Bit of Frame 15 (TSa4F15) Bit 6: Sa7 Bit of Frame 13 (TSa7F13) Bit 5: Sa7 Bit of Frame 11 (TSa7F11) Bit 4: Sa7 Bit of Frame 9 (TSa7F9) Bit 3: Sa7 Bit of Frame 7 (TSa7F7) Bit 2: Sa7 Bit of Frame 5 (TSa7F5) Bit 1: Sa7 Bit of Frame 3 (TSa7F3) Bit 0: Sa7 Bit of Frame 1 (TSa7F1) Register Name: Register Description: Register Address: E1TSa8 (E1 Mode Only) Transmit Sa8 Bits Register 16Dh + (200h x (n - 1)) : where n = 1 to 8 6 TSa8F13 0 5 TSa8F11 0 4 TSa8F9 0 3 TSa8F7 0 2 TSa8F5 0 1 TSa8F3 0 0 TSa8F1 0 Bit # Name Default 7 TSa8F15 0 Bit 7: Sa8 Bit of Frame 15 (TSa8F15) Bit 6: Sa8 Bit of Frame 13 (TSa8F13) Bit 5: Sa8 Bit of Frame 11 (TSa8F11) Bit 4: Sa8 Bit of Frame 9 (TSa8F9) Bit 3: Sa8 Bit of Frame 7 (TSa8F7) Bit 2: Sa8 Bit of Frame 5 (TSa8F5) Bit 1: Sa8 Bit of Frame 3 (TSa8F3) Bit 0: Sa8 Bit of Frame 1 (TSa8F1) 203 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TMMR Transmit Master Mode Register 180h + (200h x (n - 1)) : where n = 1 to 8 6 INIT_DONE 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 SFTRST 0 0 T1/E1 0 Bit # Name Default 7 FRM_EN 0 Bit 7: Framer Enable (FRM_EN). This bit must be set to the desired state before writing INIT_DONE. 0 = Framer disabled--held in low-power state. 1 = Framer enabled--all features active. Bit 6: Initialization Done (INIT_DONE). The user must set this bit once he has written the configuration registers. The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the DS26518 will check the FRM_EN bit and, if enabled, will begin operation based on the initial configuration. Bit 1: Soft Reset (SFTRST). Level sensitive "soft" reset. Should be taken high, then low to reset the transceiver. 0 = Normal operation. 1 = Reset the transceiver. Note: This reset does not clear the registers. Bit 0: Transmitter T1/E1 Mode Select (T1/E1). Sets operating mode for transmitter only! This bit must be written with the desired value prior to setting INIT_DONE. 0 = T1 operation. 1 = E1 operation. 204 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TCR1 (T1 Mode) Transmit Control Register 1 181h + (200h x (n - 1)) : where n = 1 to 8 6 TFPT 0 5 TCPT 0 4 TSSE 0 3 GB7S 0 2 TB8ZS 0 1 TAIS 0 0 TRAI 0 Bit # Name Default 7 TJC 0 Note: See TCR1 for E1 Mode. Bit 7: Transmit Japanese CRC-6 Enable (TJC) 0 = Use ANSI/AT&T:ITU-T CRC-6 calculation (normal operation). 1 = Use Japanese standard JT-G704 CRC-6 calculation. Bit 6: Transmit F-Bit Pass Through (TFPT) 0 = F bits sourced internally. 1 = F bits sampled at TSERn (T1.TCR2.7 TFDLS must be programmed to 0). Bit 5: Transmit CRC Pass Through (TCPT) 0 = Source CRC-6 bits internally. 1 = CRC-6 bits sampled at TSERn during F-bit time. Bit 4: Transmit Software Signaling Enable (TSSE). This function is enabled by TB7ZS (T1.TCR2.0). 0 = Do not source signaling data from the TS1-16 registers regardless of the SSIE1-4 registers. The SSIE1-4 registers still define which channels are to have B7 stuffing performed. 1 = Source signaling data as enabled by the SSIE1-4 registers. Bit 3: Global Bit 7 Stuffing (GB7S). This function is enabled by TB7ZS (T1.TCR2.0). 0 = Allow the SSIE1-4 registers to determine which channels containing all zeros are to be bit 7 stuffed. 1 = Force bit 7 stuffing in all zero byte channels of that port, regardless of how the SSIE1-4 registers are programmed. Bit 2: Transmit B8ZS Enable (TB8ZS) 0 = B8ZS disabled. 1 = B8ZS enabled. Bit 1: Transmit Alarm Indication Signal (TAIS) 0 = Transmit data normally. 1 = Transmit an unframed all-ones code at TTIPn and TRINGn. Bit 0: Transmit Remote Alarm Indication (TRAI) 0 = Do not transmit remote alarm. 1 = Transmit remote alarm. 205 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TCR1 (E1 Mode) Transmit Control Register 1 181h + (200h x (n - 1)) : where n = 1 to 8 6 T16S 0 5 TG802 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TAIS 0 0 TCRC4 0 Bit # Name Default 7 TTPT 0 Note: See TCR1 for T1 Mode. Bit 7: Transmit Time Slot 0 Pass Through (TTPT) 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the E1TAF and E1TNAF registers. 1 = FAS bits/Sa bits/Remote Alarm sourced from TSERn. Bit 6: Transmit Time Slot 16 Data Select (T16S). See Section 9.9.4 on software signaling. 0 = Time slot 16 determined by the SSIE1-4 and THSCS1-4 registers. 1 = Source time slot 16 from TS1-16 registers. Bit 5: Transmit G.802 Enable (TG802). See Section 11.4. 0 = Do not force TCHBLKn high during bit 1 of time slot 26. 1 = Force TCHBLKn high during bit 1 of time slot 26. Bit 4: Transmit International Bit Select (TSiS) 0 = Sample Si bits at TSERn pin. 1 = Source Si bits from E1TAF and E1TNAF registers (in this mode, TCR1.7 must be set to 0). Bit 3: Transmit Signaling All Ones (TSA1) 0 = Normal operation. 1 = Force time slot 16 in every frame to all ones. Bit 2: Transmit HDB3 Enable (THDB3) 0 = HDB3 disabled. 1 = HDB3 enabled. Bit 1: Transmit AIS (TAIS) 0 = Transmit data normally. 1 = Transmit an unframed all-ones code at TTIPn and TRINGn. Bit 0: Transmit CRC-4 Enable (TCRC4) 0 = CRC-4 disabled. 1 = CRC-4 enabled. 206 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1.TCR2 (T1 Mode) Transmit Control Register 2 182h + (200h x (n - 1)) : where n = 1 to 8 6 TSLC96 0 5 TDDSEN 0 4 FBCT2 0 3 FBCT1 0 2 TRAIS 0 1 -- 0 0 TB7ZS 0 Bit # Name Default 7 TFDLS 0 Note: See E1.TCR2 for E1 Mode. Bit 7: TFDL Register Select (TFDLS) 0 = Source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (T1.TCR2.6). 1 = Source FDL or Fs bits from the internal HDLC controller. Bit 6: Transmit SLC-96 (TSLC96). Set this bit to a one in SLC-96 framing applications. Must be set to source the SLC-96 alignment pattern and data from the T1TSLC1-3 registers. See Section 9.9.4.3 for details. 0 = SLC-96 insertion disabled. 1 = SLC-96 insertion enabled. Bit 5: Transmit DDS Zero Suppression Enable (TDDSEN) 0 = No DDS stuffing. 1 = DDS stuffing enabled. Force zero code 10011000 in all zero byte channels based on the channel select registers TDDS1-3. Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set. Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft (D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization. Bit 2: Transmit RAI Select (TRAIS) 0 = Transmit RAI is T1. D4--Zeros in bit 2 of all channels. ESF--00FF pattern in the FDL. 1 = Transmit RAI is J1. D4--A one in the S-bit position of frame 12. ESF--All ones in FDL. Note: This bit only selects the type of remote alarm to send. To enable transmission of remote alarm, set TCR1.TRAI. Bit 0: Transmit-Side Bit 7 Zero Suppression Enable (TB7ZS) 0 = No stuffing occurs. 1 = Force bit 7 to a one as determined by the GB7S bit at TCR1.3. 207 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1.TCR2 (E1 Mode) Transmit Control Register 2 182h + (200h x (n - 1)) : where n = 1 to 8 6 AAIS 0 5 ARA 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 -- 0 Bit # Name Default 7 AEBE 0 Note: See T1.TCR2 for T1 Mode. Bit 7: Automatic E-Bit Enable (AEBE) 0 = E-bits not automatically set in the transmit direction. 1 = E-bits automatically set in the transmit direction. Bit 6: Automatic AIS Generation (AAIS) 0 = Disabled 1 = Enabled Bit 5: Automatic Remote Alarm Generation (ARA) 0 = Disabled 1 = Enabled 208 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TCR3 Transmit Control Register 3 183h + (200h x (n - 1)) : where n = 1 to 8 6 -- -- 0 5 TCSS1 TCSS1 0 4 TCSS0 TCSS0 0 3 MFRS MFRS 0 2 TFM -- 0 1 IBPV IBPV 0 0 TLOOP CRC4 0 Bit # Name Default 7 -- -- 0 Bits 5 and 4 : Transmit Clock Source Select 1 and 0 (TCSS[1:0]) TCSS1 0 0 1 1 TCSS0 0 1 0 1 Transmit Clock Source The TCLKn pin is always the source of transmit clock. Switch to the clock present at RCLKn when the signal at the TCLKn pin fails to transition after 1 channel time. Reserved. Use the signal present at RCLKn as the transmit clock. The TCLKn pin is ignored (loop time). Bit 3: Multiframe Reference Select (MFRS). This bit selects the source for the transmit formatter multiframe boundary. 0 = Normal Operation. Transmit multiframe boundary is determined by 'line-side' counters referenced to TSYNCn when TSYNCn is an input. Free-running when TSYNCn is an output. 1 = Pass-Forward Operation. Tx multiframe boundary determined by 'system-side' counters referenced to TSSYNCIOn (input mode3), which is then passed forward to the line side clock domain. This mode can only be used when the transmit elastic store is enabled with a synchronous backplane (i.e., no frame slips allowed). This mode must be used to allow Tx hardware signaling insertion while the Tx elastic store is enabled. Bit 2: Transmit Frame Mode Select (TFM) (T1 Mode Only) 0 = ESF framing mode. 1 = D4 framing mode. Bit 1: Insert BPV (IBPV). A 0-to-1 transition on this bit will cause a single Bipolar Violation (BPV) to be inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Bit 0 (T1 Mode): Transmit Loop Code Enable (TLOOP). See Section 9.9.15 for details. 0 = Transmit data normally. 1 = Replace normal transmitted data with repeating code as defined in registers T1TCD1 and T1TCD2. Bit 0 (E1 Mode): CRC-4 Recalculate (CRC4R) 0 = Transmit CRC-4 generation and insertion operates in normal mode. 1 = Transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method. 209 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TIOCR Transmit I/O Configuration Register 184h + (200h x (n - 1)) : where n = 1 to 8 6 TSYNCINV TSYNCINV Bit # Name Default 7 TCLKINV TCLKINV 0 5 TSSYNCINV TSSYNCINV 0 0 4 TSCLKM TSCLKM 0 3 TSSM TSSM 0 2 TSIO TSIO 0 1 TSDW -- 0 0 TSM TSM 0 Bit 7: TCLKn Invert (TCLKINV) 0 = No inversion. 1 = Invert. Bit 6: TSYNCn Invert (TSYNCINV) 0 = No inversion. 1 = Invert. Bit 5: TSSYNCIOn (Input Mode Only) Invert (TSSYNCINV) 0 = No inversion. 1 = Invert. Bit 4: TSYSCLKn Mode Select (TSCLKM) 0 = If TSYSCLKn is 1.544MHz. 1 = If TSYSCLKn is 2.048/4.096/8.192MHz or IBO enabled (see Section 9.8.2 for details on IBO function). Bit 3: TSSYNCIOn Mode Select (TSSM). Selects frame or multiframe mode for the TSSYNCIOn pin. 0 = Frame mode. 1 = Multiframe mode. Bit 2: TSYNCn I/O Select (TSIO) 0 = TSYNCn is an input. 1 = TSYNCn is an output. Bit 1: TSYNCn Double-Wide (TSDW) (T1 Mode Only) (Note: This bit must be set to zero when TSM = 1 or when TSIO = 0.) 0 = Do not pulse double-wide in signaling frames. 1 = Do pulse double-wide in signaling frames. Bit 0: TSYNCn Mode Select (TSM). Selects frame or multiframe mode for the TSYNCn pin. 0 = Frame mode. 1 = Multiframe mode. 210 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TESCR Transmit Elastic Store Control Register 185h + (200h x (n - 1)) : where n = 1 to 8 6 TGCLKEN 0 5 -- 0 4 TSZS 0 3 TESALGN 0 2 TESR 0 1 TESMDM 0 0 TESE 0 Bit # Name Default 7 TDATFMT 0 Note: Bits 6 and 7 are used for fractional backplane support. See Section 9.8.5. Bit 7: Transmit Channel Data Format (TDATFMT) 0 = 64kbps (data contained in all 8 bits). 1 = 56kbps (data contained in 7 out of the 8 bits). Bit 6: Transmit Gapped Clock Enable (TGCLKEN) 0 = TCHCLK functions normally. 1 = Enable gapped bit clock output on TCHCLKn. Bit 4: Transmit Slip Zone Select (TSZS). This bit determines the minimum distance allowed between the elastic store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1 conversion applications. 0 = Force a slip at 9 bytes or less of separation (used for clustered blank channels). 1 = Force a slip at 2 bytes or less of separation (used for distributed blank channels). Bit 3: Transmit Elastic Store Align (TESALGN). Setting this bit from a zero to a one will force the transmit elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after TSYSCLKn has been applied and is stable. Must be cleared and set again for a subsequent align. Bit 2: Transmit Elastic Store Reset (TESR). Setting this bit from a zero to a one will force the read pointer into the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will move back to opposite frames. Should be toggled after TSYSCLKn has been applied and is stable. Do not leave this bit set high. Bit 1: Transmit Elastic Store Minimum Delay Mode (TESMDM) 0 = Elastic stores operate at full two-frame depth. 1 = Elastic stores operate at 32-bit depth. Bit 0: Transmit Elastic Store Enable (TESE) 0 = Elastic store is bypassed. 1 = Elastic store is enabled. 211 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TCR4 Transmit Control Register 4 186h + (200h x (n - 1)) : where n = 1 to 8 6 BINV1 BINV1 0 5 BINV0 BINV0 0 4 TJBEN TJBEN 0 3 TRAIM -- 0 2 TAISM -- 0 1 TC1 -- 0 0 TC0 -- 0 Bit # Name Default 7 uALAW uALAW 0 Bit 7: u-Law or A-Law Digital Milliwatt Code Select (uALAW) 0 = u-law code is inserted based on TDMWEx registers. 1 = A-law code is inserted based on TDMWEx registers. Bits 6 and 5: Transmit Bit Inversion (BINV[1:0]) 00 = No inversion. 01 = Invert framing. 10 = Invert signaling. 11 = Invert payload. Bit 4: Transmit Jammed Bit 8 Suppression Enable (TJBEN) 0 = No stuffing enabled. 1 = Jammed Bit 8 Suppression enabled. This forces bit 8 to a one as determined by TJBE1-4 registers and bit 7 to a one in T1 signaling frames. Bits 3: Transmit RAI Mode (TRAIM) (T1 Mode Only). Determines the pattern sent when TRAI (TCR1.0) is activated in ESF frame mode only. 0 = Transmit normal RAI when TCR1.RAI = 1 1 = If T1 ESF mode, transmit RAI-CI (T1.403) when TCR1.RAI = 1 Bits 2 : Transmit AIS Mode (TAISM) (T1 Mode Only). Determines the pattern sent when TAIS (TCR1.1) is activated. 0 = Transmit normal AIS (unframed all ones) upon activation with TCR1.1. 1 = Transmit AIS-CI (T1.403) upon activation with TCR1.1. Bits 1 and 0 : Transmit Code Length Definition Bits (TC[1:0]) (T1 Mode Only) TC1 0 0 1 1 TC0 0 1 0 1 Length Selected 5 bits 6 bits : 3 bits 7 bits 16 bits : 8 bits : 4 bits : 2 bits : 1 bit 212 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: THFC Transmit HDLC FIFO Control Register 187h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 TFLWM1 0 0 TFLWM0 0 Bit # Name Default 7 -- 0 Bits 1 and 0: Transmit HDLC FIFO Low Watermark Select (TFLWM[1:0]) TFLWM1 0 0 1 1 TFLWM0 0 1 0 1 Transmit FIFO Watermark 4 bytes 16 bytes 32 bytes 48 bytes Register Name: Register Description: Register Address: TIBOC Transmit Interleave Bus Operation Control Register 188h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 IBOSEL 0 3 IBOEN 0 2 -- 0 1 -- 0 0 -- 0 Bit # Name Default 7 -- 0 Bit 4: Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode. 0 = Channel Interleave. 1 = Frame Interleave. Bit 3: Interleave Bus Operation Enable (IBOEN) 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Register Name: Register Description: Register Address: TDS0SEL Transmit DS0 Channel Monitor Select Register 189h + (200h x (n - 1)) : where n = 1 to 8 6 -- Bit # Name Default 7 -- 5 -- 0 0 0 4 TCM4 0 3 TCM3 0 2 TCM2 0 1 TCM1 0 0 TCM0 0 Bits 4 to 0: Transmit Channel Monitor Bits (TCM[4:0]). TCM0 is the LSB of a 5-bit channel select that determines which transmit channel data will appear in the TDS0M register. Channels 1 through 32 are represented by a 5-bit BCD code from 0 to 31. TCM[0:4] = all 0s selects channel 1, TCM[0:4] = 11111 selects channel 32. 213 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TXPC Transmit Expansion Port Control Register 18Ah + (200h x (n - 1)) : where n = 1 to 8 6 -- Bit # Name Default 7 -- 5 -- 4 -- 3 -- 0 0 0 0 0 2 TBPDIR 0 1 TBPFUS 0 0 TBPEN 0 Bit 2: Transmit BERT Port Direction Control (TBPDIR) 0 = Normal (line) operation. Transmit BERT port sources data into the transmit path. 1 = System (backplane) operation. Transmit BERT port sources data into the receive path (RSERn). In this mode, the data from the BERT is muxed into the receive path. Bit 1: Transmit BERT Port Framed/Unframed Select (TBPFUS) 0 = The DS26518's transmit BERT will not clock data into the F-bit position (framed). 1 = The DS26518's transmit BERT will clock data into the F-bit position (unframed). Bit 0: Transmit BERT Port Enable (TBPEN) 0 = Transmit BERT port is not active. 1 = Transmit BERT port is active. 214 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TBPBS Transmit BERT Port Bit Suppress Register 18Bh + (200h x (n - 1)) : where n = 1 to 8 6 BPBSE7 0 5 BPBSE6 0 4 BPBSE5 0 3 BPBSE4 0 2 BPBSE3 0 1 BPBSE2 0 0 BPBSE1 0 Bit # Name Default 7 BPBSE8 0 Bit 7: Transmit Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Transmit Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used. Bit 5: Transmit Channel Bit 6 Suppress (BPBSE6). Set to one to stop this bit from being used. Bit 4: Transmit Channel Bit 5 Suppress (BPBSE5). Set to one to stop this bit from being used. Bit 3: Transmit Channel Bit 4 Suppress (BPBSE4). Set to one to stop this bit from being used. Bit 2: Transmit Channel Bit 3 Suppress (BPBSE3). Set to one to stop this bit from being used. Bit 1: Transmit Channel Bit 2 Suppress (BPBSE2). Set to one to stop this bit from being used. Bit 0: Transmit Channel Bit 1 Suppress (BPBSE1). LSB of the channel. Set to one to stop this bit from being used. Register Name: Register Description: Register Address: TSYNCC Transmit Synchronizer Control Register 18Eh + (200h x (n - 1)) : where n = 1 to 8 6 -- -- 0 5 -- -- 0 4 -- -- 0 3 -- CRC4 0 2 TSEN TSEN 0 1 SYNCE SYNCE 0 0 RESYNC RESYNC 0 Bit # Name Default 7 -- -- 0 Bit 3: CRC-4 Enable (CRC4) (E1 Mode Only) 0 = Do not search for the CRC-4 multiframe word. 1 = Search for the CRC-4 multiframe word. Bit 2: Transmit Synchronizer Enable (TSEN) 0 = Transmit synchronizer disabled. 1 = Transmit synchronizer enabled. Bit 1: Sync Enable (SYNCE) 0 = Auto resync enabled. 1 = Auto resync disabled. Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the transmit-side framer is initiated. Must be cleared and set again for a subsequent resync. 215 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TLS1 Transmit Latched Status Register 1 190h + (200h x (n - 1)) : where n = 1 to 8 6 TESEM TESEM 0 5 TSLIP TSLIP 0 4 TSLC96 -- 0 3 -- TAF 0 2 TMF TMF 0 1 LOTCC LOTCC 0 0 LOTC LOTC 0 Bit # Name Default 7 TESF TESF 0 Note: All bits in this register are latched and can cause interrupts. Bit 7: Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted. Bit 6: Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a frame is repeated. Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP). Set when the transmit elastic store has either repeated or deleted a frame. Bit 4: Transmit SLC-96 Multiframe Event (TSLC96) (T1 Mode Only). When enabled by T1.TCR2.6, this bit will set once per SLC-96 multiframe (72 frames) to alert the host that new data may be written to the T1TSLC1-3 registers. See Section 9.9.4.3 for more information. Bit 3: Transmit Align Frame Event (TAF) (E1 Mode Only). Set every 250s to alert the host that the E1TAF and E1TNAF registers need to be updated. Bit 2: Transmit Multiframe Event (TMF). In T1 mode, this bit is set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries. In E1 operation, this but is set every 2ms (regardless if CRC-4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated. Bit 1: Loss of Transmit Clock Condition Clear (LOTCC). Set when the LOTC condition has cleared (a clock has been sensed at the TCLKn pin). Bit 0: Loss of Transmit Clock Condition (LOTC). Set when the TCLKn pin has not transitioned for approximately 3 clock periods. Will force the LOTC pin high if enabled. This bit can be cleared by the host even if the condition is still present. The LOTC pin will remain high while the condition exists, even if the host has cleared the status bit. If enabled by TIM1.0, the INTB pin will transition low when this bit is set, and transition high when this bit is cleared (if no other unmasked interrupt conditions exist). 216 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TLS2 Transmit Latched Status Register 2 (HDLC) 191h + (200h x (n - 1)) : where n = 1 to 8 6 -- -- 0 5 -- -- 0 4 TFDLE -- 0 3 TUDR TUDR 0 2 TMEND TMEND 0 1 TLWMS TLWMS 0 0 TNFS TNFS 0 Bit # Name Default 7 -- -- 0 Note: All bits in this register are latched and can create interrupts. Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only). Set when the TFDL register has shifted out all 8 bits. Useful if the user wants to manually use the TFDL register to send messages, instead of using the HDLC or BOC controller circuits. Bit 3: Transmit FIFO Underrun Event (TUDR). Set when the transmit FIFO empties out without having seen the TMEND bit set. An abort is automatically sent. Bit 2: Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a message. Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS). Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the transmit low watermark bits (TLWM), rising edge detect of TLWM. Bit 0: Transmit FIFO Not Full Set Condition (TNFS). Set when the transmit 64-byte FIFO has at least one empty byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full. Register Name: Register Description: Register Address: TLS3 Transmit Latched Status Register 3 (Synchronizer) 192h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 LOF 0 0 LOFD 0 Bit # Name Default 7 -- 0 Note: Some bits in this register are latched and can create interrupts. Bit 1: Loss of Frame (LOF). A real-time bit that indicates that the transmit synchronizer is searching for the sync pattern in the incoming data stream. Bit 0: Loss Of Frame Synchronization Detect (LOFD). This latched bit is set when the transmit synchronizer is searching for the sync pattern in the incoming data stream. 217 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TIIR Transmit Interrupt Information Register 19Fh + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 TLS3 0 1 TLS2 0 0 TLS1 0 Bit # Name Default 7 -- 0 The interrupt information register provides an indication of which status registers are generating an interrupt. When an interrupt occurs, the host can read TIIR to quickly identify which of the transmit status registers are causing the interrupt(s). These are real-time registers in that the bits will clear once the appropriate interrupt has been serviced and cleared. Bit 2: Transmit Latched Status Register 3 Interrupt Status (TLS3) 0 = No interrupt pending. 1 = Interrupt pending. Bit 1: Transmit Latched Status Register 2 Interrupt Status (TLS2) 0 = No interrupt pending. 1 = Interrupt pending. Bit 0: Transmit Latched Status Register 1 Interrupt Status (TLS1) 0 = No interrupt pending. 1 = Interrupt pending. 218 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TIM1 Transmit Interrupt Mask Register 1 1A0h + (200h x (n - 1)) : where n = 1 to 8 6 TESEM TESEM 0 5 TSLIP TSLIP 0 4 TSLC96 -- 0 3 -- TAF 0 2 TMF TMF 0 1 LOTCC LOTCC 0 0 LOTC LOTC 0 Bit # Name Default 7 TESF TESF 0 Bit 7: Transmit Elastic Store Full Event (TESF) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Transmit Elastic Store Empty Event (TESEM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Transmit SLC96 Multiframe Event (TSLC96) (T1 Mode Only) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Transmit Align Frame Event (TAF) (E1 Mode Only) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Transmit Multiframe Event (TMF) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: Loss of Transmit Clock Clear Condition (LOTCC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Loss of Transmit Clock Condition (LOTC) 0 = Interrupt masked. 1 = Interrupt enabled. 219 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TIM2 Transmit Interrupt Mask Register 2 1A1h + (200h x (n - 1)) : where n = 1 to 8 6 -- -- 0 5 -- -- 0 4 TFDLE -- 0 3 TUDR TUDR 0 2 TMEND TMEND 0 1 TLWMS TLWMS 0 0 TNFS TNFS 0 Bit # Name Default 7 -- -- 0 Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Transmit FIFO Underrun Event (TUDR) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Transmit Message End Event (TMEND) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0: Transmit FIFO Not Full Set Condition (TNFS) 0 = Interrupt masked. 1 = Interrupt enabled. Register Name: Register Description: Register Address: TIM3 Transmit Interrupt Mask Register 3 (Synchronizer) 1A2h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 LOFD 0 Bit # Name Default 7 -- 0 Bit 0: Loss Of Frame Synchronization Detect (LOFD) 0 = Interrupt masked. 1 = Interrupt enabled. 220 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1TCD1 (T1 Mode Only) Transmit Code Definition Register 1 1ACh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Bit 7: Transmit Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Transmit Code Definition Bit 6 (C6) Bit 5: Transmit Code Definition Bit 5 (C5) Bit 4: Transmit Code Definition Bit 4 (C4) Bit 3: Transmit Code Definition Bit 3 (C3) Bit 2: Transmit Code Definition Bit 2 (C2). A Don't Care if a 5-bit length is selected. Bit 1: Transmit Code Definition Bit 1 (C1). A Don't Care if a 5- or 6-bit length is selected. Bit 0: Transmit Code Definition Bit 0 (C0). A Don't Care if a 5-, 6-, or 7-bit length is selected. Register Name: Register Description: Register Address: T1TCD2 (T1 Mode Only) Transmit Code Definition Register 2 1ADh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit # Name Default 7 C7 0 Bit 7: Transmit Code Definition Bit 7 (C7). A Don't Care if a 5-, 6-, or 7-bit length is selected. Bit 6: Transmit Code Definition Bit 6 (C6). A Don't Care if a 5-, 6-, or 7-bit length is selected. Bit 5: Transmit Code Definition Bit 5 (C5). A Don't Care if a 5-, 6-, or 7-bit length is selected. Bit 4: Transmit Code Definition Bit 4 (C4). A Don't Care if a 5-, 6-, or 7-bit length is selected. Bit 3: Transmit Code Definition Bit 3 (C3). A Don't Care if a 5-, 6-, or 7-bit length is selected. Bit 2: Transmit Code Definition Bit 2 (C2). A Don't Care if a 5-, 6-, or 7-bit length is selected. Bit 1: Transmit Code Definition Bit 1 (C1). A Don't Care if a 5-, 6-, or 7-bit length is selected. Bit 0: Transmit Code Definition Bit 0 (C0). A Don't Care if a 5-, 6-, or 7-bit length is selected. 221 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TRTS2 Transmit Real-Time Status Register 2 (HDLC) 1B1h + (200h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 TEMPTY 0 2 TFULL 0 1 TLWM 0 0 TNF 0 Bit # Name Default 7 -- 0 Note: All bits in this register are real time. Bit 3: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty. Bit 2: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full. Bit 1: Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the transmit low watermark bits (TLWM). Bit 0: Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least one byte available. Register Name: Register Description: Register Address: TFBA Transmit HDLC FIFO Buffer Available Register 1B3h + (200h x (n - 1)) : where n = 1 to 8 6 TFBA6 0 5 TFBA5 0 4 TFBA4 0 3 TFBA3 0 2 TFBA2 0 1 TFBA1 0 0 TFBA0 0 Bit # Name Default 7 -- 0 Bits 6 to 0: Transmit FIFO Bytes Available (TFBA6 to TFBA0). TFBA0 is the LSB. Register Name: Register Description: Register Address: THF Transmit HDLC FIFO Register 1B4h + (200h x (n - 1)) : where n = 1 to 8 6 THD6 0 5 THD5 0 4 THD4 0 3 THD3 0 2 THD2 0 1 THD1 0 0 THD0 0 Bit # Name Default 7 THD7 0 Bit 7: Transmit HDLC Data Bit 7 (THD7). MSB of an HDLC packet data byte. Bit 6: Transmit HDLC Data Bit 6 (THD6) Bit 5: Transmit HDLC Data Bit 5 (THD5) Bit 4: Transmit HDLC Data Bit 4 (THD4) Bit 3: Transmit HDLC Data Bit 3 (THD3) Bit 2: Transmit HDLC Data Bit 2 (THD2) Bit 1: Transmit HDLC Data Bit 1 (THD1) Bit 0: Transmit HDLC Data Bit 0 (THD0). LSB of an HDLC packet data byte. 222 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TDS0M Transmit DS0 Monitor Register 1BBh + (200h x (n - 1)) : where n = 1 to 8 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bit # Name Default 7 B1 0 Bits 7 to 0: Transmit DS0 Channel Bits (B[1:8]). Transmit channel data that has been selected by the TDS0SEL register. B8 is the LSB of the DS0 channel (last bit to be transmitted). Register Name: Register Description: Register Address: TBCS1, TBCS2, TBCS3, TBCS4 Transmit Blank Channel Select Registers 1 to 4 1C0h, 1C1h, 1C2h, 1C3h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Named (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 TBCS1 TBCS2 TBCS3 TBCS4 (E1 Mode Only) Bits 7 to 0: Transmit Blank Channel Select for Channels 1 to 32 (CH[1:32]) 0 = Transmit TSERn data from this channel. 1 = Ignore TSERn data from this channel. Note that when two or more sequential channels are chosen to be ignored, the receive slip zone select bit should be set to zero. If the ignore channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29) then the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications. 223 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TCBR1, TCBR2, TCBR3, TCBR4 Transmit Channel Blocking Registers 1 to 4 1C4h, 1C5h, 1C6h, 1C7h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 (F-bit) Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 TCBR1 TCBR2 TCBR3 TCBR4 (E1 Mode Only)* Bits 7 to 0: Transmit Channels 1 to 32 Channel Blocking Control Bits (CH[1:32]). 0 = Force the TCHBLKn pin to remain low during this channel time. 1 = Force the TCHBLKn pin high during this channel time. * Note that TCBR4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking signal for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the TCHBLKn signal will pulse high during the F-bit time: TCBR4.0 = 0, do not pulse TCHBLKn during the F-bit. TCBR4.0 = 1, pulse TCHBLKn during the F-bit. In this mode TCBR4.1 to TCBR4.7 should be set to 0. Register Name: Register Description: Register Address: (MSB) 7 CH8 CH16 CH24 CH32 THSCS1, THSCS2, THSCS3, THSCS4 Transmit Hardware-Signaling Channel Select Registers 1 to 4 1C8h, 1C9h, 1CAh, 1CBh + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 THSCS1 THSCS2 THSCS3 THSCS4 (E1 Mode Only)* Bits 7 to 0: Transmit Hardware-Signaling Channel Select for Channels 1 to 32 (CH[1:32]). These bits determine which channels have signaling data inserted from the TSIGn pin into the TSERn PCM data. 0 = Do not source signaling data from the TSIGn pin for this channel. 1 = Source signaling data from the TSIGn pin for this channel. * Note that THSCS4 is only used in 2.048MHz backplane applications. 224 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TGCCS1, TGCCS2, TGCCS3, TGCCS4 Transmit Gapped Clock Channel Select Registers 1 to 4 1CCh, 1CDh, 1CEh, 1CFh + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 (F-bit) Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 TGCCS1 TGCCS2 TGCCS3 TGCCS4 (E1 Mode Only)* Bits 7 to 0: Transmit Channels 1 to 32 Gapped Clock Channel Select Bits (CH[1:32]) 0 = no clock is present on TCHCLK during this channel time 1 = force a clock on TCHCLK during this channel time. The clock will be synchronous with TCLKn if the elastic store is disabled, and synchronous with TSYSCLKn if the elastic store is enabled. * Note that TGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on TCHCLK for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on TCHCLK during the F-bit time: TGCCS4.0 = 0, do not generate a clock during the F-bit. TGCCS4.0 = 1, generate a clock during the F-bit. In this mode TGCCS4.1 to TGCCS4.7 should be set to 0. Register Name: Register Description: Register Address: PCL1, PCL2, PCL3, PCL4 Per-Channel Loopback Enable Registers 1 to 4 1D0h, 1D1h, 1D2h, 1D3h + (200h x (n - 1)) : where n = 1 to 8 (LSB) 0 CH1 CH9 CH17 CH25 Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 PCL1 PCL2 PCL3 PCL4 (E1 Mode Only) Bits 7 to 0: Per-Channel Loopback Enable for Channels 1 to 32 (CH[1:32]) 0 = Loopback disabled. 1 = Enable loopback. Source data from the corresponding receive channel. 225 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TBPCS1, TBPCS2, TBPCS3, TBPCS4 Transmit BERT Port Channel Select Registers 1D4h, 1D5h, 1D6h, 1D7h + (200h x (n - 1)) : where n = 1 to 8 (LSB) CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 CH1 CH9 CH17 CH25 TBPCS1 TBPCS2 TBPCS3 TBPCS4 (E1 Mode Only) (MSB) Bit # Name CH8 CH16 CH24 CH32 Setting any of the CH[1:32] bits in the TBPCS1 to TBPCS4 registers will enable the transmit BERT clock for the associated channel time, and allow mapping of the selected channel data out of the receive BERT port. Multiple or all channels may be selected simultaneously. 226 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.5 LIU Register Definitions Table 10-15. LIU Register Set ADDRESS 1000h 1001h 1002h 1003h 1004h 1005h 1006h 1007h 1008h 1009h-101Fh NAME LTRCR LTIPSR LMCR LRSR LSIMR LLSR LRSL LRISMR LRCR -- DESCRIPTION LIU Transmit Receive Control Register LIU Transmit Impedance and Pulse Shape Selection Register LIU Maintenance Control Register LIU Real Status Register LIU Status Interrupt Mask Register LIU Latched Status Register LIU Receive Signal Level Register LIU Receive Impedance and Sensitivity Monitor Register LIU Receive Control Register Reserved R/W R/W R/W R/W R R/W R/W R R/W R/W -- Note: Reserved registers should only be written with all zeros. 227 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Addresses: LTRCR LIU Transmit Receive Control Register 1000h + (20h x (n - 1)) : where n = 1 to 8 6 RHPM 0 5 JADS1 0 4 JADS0 0 3 JAPS1 0 2 JAPS0 0 1 T1J1E1S 0 0 LSC 0 Bit # Name Default 7 -- 0 Bit 6: Receive Hitless Protection Mode (RHPM). 0 = Normal operation using software for hitless protection (RIMPON). 1 = Hitless protection switching mode using TXENABLE pin. If the TXENABLE pin is low and this bit is set to one, the receive LIU will present a high impedance to the line, overriding the receive impedance selection register bits LRISMR.RIMPM[2:0]. Bits 5 and 4 : Jitter Attenuator Depth Select (JADS[1:0]) JADS1 0 0 1 1 JADS0 0 1 0 1 FUNCTION Jitter attenuator FIFO depth 128 bits. Jitter attenuator FIFO depth 64 bits. Jitter attenuator FIFO depth 32 bits. Jitter attenuator FIFO depth 16 bits (used for delay sensitive applications). Bits 3 and 2: Jitter Attenuator Position Select (JAPS[1:0]). These bits are used to select the position of the jitter attenuator. JAPS1 0 0 1 1 JAPS0 0 1 0 1 FUNCTION Jitter attenuator in the receive path. Jitter attenuator in the transmit path. Jitter attenuator disabled. Jitter attenuator disabled. Bit 1: T1J1E1 Selection (T1J1E1S). This bit configures the LIU for E1 or T1/J1 operation. 0 = E1 1 = T1 or J1 Bit 0: LOS Selection Criteria (LSC). This bit is used for LIU LOS selection criteria. E1 Mode 0 = G.775 1 = ETS 300 233 T1/J1 Mode 0 = T1.231 1 = T1.231 228 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LTIPSR LIU Transmit Impedance and Pulse Shape Selection Register 1001h + (20h x (n - 1)) : where n = 1 to 8 6 TIMPTON 0 5 TIMPL1 0 4 TIMPL0 0 3 -- 0 2 L2 0 1 L1 0 0 L0 0 Bit # Name Default 7 TG703 0 Bit 7: Transmit G.703 Synchronization Clock (TG703) 0 = Normal transmitter mode. 1 = G.703 2.048MHz clock transmitted on TTIPn and TRINGn. Bit 6: Transmit Impedance On (TIMPTON) 0 = Disable transmit terminating impedance. 1 = Enable transmit terminating impedance. Bits 5 and 4: Transmit Load Impedance 1 and 0 (TIMPL[1:0]). These bits are used to select the transmit load impedance. These must be set to match the cable impedance. Even if the Internal load impedance is turned off (via TIMPTOFF); the external cable impedance has to be specified for optimum operation. For J1 applications, use 110. See Table 10-16. Bits 2 to 0: Line Build-Out Select 2 to 0 (L[2:0]). Used to select the transmit waveshape. The waveshape has a voltage level and load impedance associated with it once the T1/J1 or E1 selection is made by settings in the LTRCR register. See Table 10-17. Table 10-16. Transmit Load Impedance Selection TIMPL1 0 0 1 1 TIMPLO 0 1 0 1 IMPEDANCE SELECTION 75 100 110 120 Table 10-17. Transmit Pulse Shape Selection L2 0 0 L1 0 0 L0 0 1 MODE E1 E1 IMPEDANCE 75 120 NOMINAL VOLTAGE 2.37V 3.0V MAX ALLOWED CABLE LOSS 0.6dB 1.2dB 1.8dB 2.4dB 3.0dB -- -- -- L2 0 0 0 0 1 1 1 1 L1 0 0 1 1 0 0 1 1 L0 0 1 0 1 0 1 0 1 MODE T1/J1 T1/J1 T1/J1 T1/J1 T1/J1 T1/J1 T1/J1 T1/J1 CABLE LENGTH DSX-1/0dB CSU, 0ft-133ft ABAM 100 DSX-1, 133ft-266ft ABAM 100 DSX-1, 266ft-399ft ABAM 100 DSX-1, 399ft-533ft ABAM 100 DSX-1, 533ft-655ft ABAM 100 -7.5dB CSU -15dB CSU -22.5dB CSU 229 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LMCR LIU Maintenance Control Register 1002h + (20h x (n - 1)) : where n = 1 to 8 6 ATAIS 0 5 LB2 0 4 LB1 0 3 LB0 0 2 TPDE 0 1 RPDE 0 0 TE 0 Bit # Name Default 7 TAIS 0 Bit 7: Manual Transmit AIS (TAIS). Alarm Indication Signal (AIS) is sent using MCLK as the reference clock. The transmit data coming from the framer is ignored. 0 = TAIS is disabled. 1 = Output an unframed all-ones pattern (AIS) at TTIPn and TRINGn. Bit : Automatic Transmit AIS (ATAIS) 0 = ATAIS is disabled. 1 = Automatically transmit AIS on the occurrence of an LIU LOS. Bits 5 to 3: Loopback Selection (LB[2:0]. See Figure 9-26 for more details on each loopback. LB2 0 0 0 0 1 1 1 1 LB1 0 0 1 1 0 0 1 1 LB0 0 1 0 1 0 1 0 1 Loopback Selection No loopback selected Remote Loopback 2 (includes jitter attenuator) Analog Loopback Remote Loopback 1 (no jitter attenuator) Local Loopback (includes jitter attenuator) Dual Loopback--Remote Loopback 1 and Local Loopback (jitter attenuator is included in Local Loopback) Reserved Reserved Bit 2: Transmit Power-Down Enable (TPDE) 0 = Transmitter power enabled. 1 = Transmitter powered down. TTIPn/TRINGn outputs are high impedance. Bit 1: Receiver Power-Down Enable (RPDE) 0 = Receiver power enabled. 1 = Receiver powered down. Bit 0: Transmit Enable (TE). This function is overridden by the TXENABLE pin. 0 = TTIPn/TRINGn outputs are high impedance. 1 = TTIPn/TRINGn outputs enabled. 230 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LRSR LIU Real Status Register 1003h + (20h x (n - 1)) : where n = 1 to 8 6 -- 0 5 OEQ 0 4 UEQ 0 3 RSCS 0 2 TSCS 0 1 OCS 0 0 LOSS 0 Bit # Name Default 7 -- 0 Bit 5: Over Equalized (OEQ). The equalizer is over equalized. This can happen if there very large unexpected resistive loss. This could result if monitor mode is used and the device is not placed in monitor mode. This indicator provides more qualitative information to the receive loss indicators. Bit 4: Under Equalized (UEQ). The equalizer is under equalized. A signal with a very high resistive gain is being applied. This indicator provides more qualitative information to the receive loss indicators. Bit 3: Receive Short-Circuit Status (RSCS). A real-time bit set when the LIU detects that the RTIPn and RRINGn inputs are short-circuited. The load resistance has to be 25 (typically) or less for short circuit detection. Bit 2: Transmit Short-Circuit Status (TSCS). A real-time bit set when the LIU detects that the TTIPn and TRINGn outputs are short-circuited. The load resistance has to be 25 (typically) or less for short circuit detection. Bit 1: Open-Circuit Status (OCS). A real-time bit that is set when the LIU detects that the TTIPn and TRINGn outputs are open-circuited. Bit 0: Loss of Signal Status (LOSS). A real-time bit that is set when the LIU detects an LOS condition at RTIPn and RRINGn. 231 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LSIMR LIU Status Interrupt Mask Register 1004h + (20h x (n - 1)) : where n = 1 to 8 6 OCCIM 0 5 SCCIM 0 4 LOSCIM 0 3 JALTSIM 0 2 OCDIM 0 1 SCDIM 0 0 LOSDIM 0 Bit # Name Default 7 JALTCIM 0 Bit 7: Jitter Attenuator Limit Trip Clear Interrupt Mask (JALTCIM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Open-Circuit Clear Interrupt Mask (OCCIM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: Short-Circuit Clear Interrupt Mask (SCCIM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Loss of Signal Clear Interrupt Mask (LOSCIM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Jitter Attenuator Limit Trip Set Interrupt Mask (JALTSIM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Open-Circuit Detect Interrupt Mask (OCDIM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1: Short-Circuit Detect Interrupt Mask (SCDIM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0 : Loss of Signal Detect Interrupt Mask (LOSDIM) 0 = Interrupt masked. 1 = Interrupt enabled. 232 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LLSR LIU Latched Status Register 1005h + (20h x (n - 1)) : where n = 1 to 8 6 OCC 0 5 SCC 0 4 LOSC 0 3 JALTS 0 2 OCD 0 1 SCD 0 0 LOSD 0 Bit # Name Default 7 JALTC 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Jitter Attenuator Limit Trip Clear (JALTC). This latched bit is set when a JA limit trip condition was detected and then removed. Bit 6: Open-Circuit Clear (OCC). This latched bit is set when an open circuit condition was detected at TTIPn and TRINGn and then removed. Bit 5: Short-Circuit Clear (SCC). This latched bit is set when a short circuit condition was detected at TTIPn and TRINGn and then removed. Bit 4: Loss of Signal Clear (LOSC). This latched bit is set when a loss of signal condition was detected at RTIPn and RRINGn and then removed. Bit 3: Jitter Attenuator Limit Trip Set (JALTS). This latched bit is set when the jitter attenuator trip condition is detected. Bit 2: Open-Circuit Detect (OCD). This latched bit is set when open-circuit condition is detected at TTIPn and TRINGn. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7). Bit 1: Short-Circuit Detect (SCD). This latched bit is set when short-circuit condition is detected at TTIPn and TRINGn. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7). Bit 0: Loss of Signal Detect (LOSD). This latched bit is set when an LOS condition is detected at RTIPn and RRINGn. 233 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LRSL LIU Receive Signal Level Register 1006h + (20h x (n - 1)) : where n = 1 to 8 6 RSL2 0 5 RLS1 0 4 RLS0 0 3 -- 0 2 -- 0 1 -- 0 0 -- 0 Bit # Name Default 7 RSL3 0 Bits 7 to 4: Receiver Signal Level 3 to 0 (RSL[3:0]). Real-time receive signal level as shown in Table 10-18. Note that the range of signal levels reported the RSL[3:0] is limited by the Equalizer Gain Limit (EGL) in short-haul applications. Table 10-18. Receive Level Indication RSL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RSL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RSL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RSL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RECEIVE LEVEL DS1/E1 (dB) > -2.5 -2.5 to -5 -5 to -7.5 -7.5 to -10 -10 to -12.5 -12.5 to -15 -15 to -17.5 -17.5 to -20 -20 to -22.5 -22.5 to 25 -25 to -27.5 -27.5 to -30 -30 to -32.5 -32.5 to -35 -35 to -37.5 < -37.5 234 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LRISMR LIU Receive Impedance and Sensitivity Monitor Register 1007h + (20h x (n - 1)) : where n = 1 to 8 6 RIMPON 0 5 -- 0 4 -- 0 3 -- 0 2 RIMPM2 0 1 RIMPM1 0 0 RIMPM0 0 Bit # Name Default 7 -- 0 Bit 6: Receive Internal Impedance Match On (RIMPON) 0 = Receive internal impedance termination is disabled (high impedance). 1 = Receive internal impedance termination is enabled. Bits 2 to 0: Receive Impedance Selection (RIMPM[2:0]). These bits are used to select the receive impedance termination. They must be set according to the cable impedance even if internal termination resistance is disabled (RIMPON = 0). See Table 10-19. Table 10-19. Receive Impedance Selection RIMPON 0 0 0 0 1 1 1 1 1 1 1 1 RIMPRM[2:0] x00 x01 x10 x11 000 001 010 011 100 101 110 111 RECEIVE IMPEDANCE SELECTED () 75 external termination (no internal impedance match) 100 external termination (no internal impedance match) 110 external termination (no internal impedance match) 120 external termination (no internal impedance match) 75, with external 120 resistor 100, with external 120 resistor 110, with external 120 resistor 120, with external 120 resistor 75 internal termination 100 internal termination 110 internal termination 120 internal termination 235 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LRCR LIU Receive Control Register 1008h + (20h x (n - 1)) : where n = 1 to 8 6 -- 0 5 -- 0 4 -- 0 3 RTR 0 2 RMONEN 0 1 RSMS1 0 0 RSMS0 0 Bit # Name Default 7 RG703 0 Bit 7: Receive G.703 Clock (RG703). If this bit is set, the receiver expects a 2.048MHz or 1.544MHz clock from the RTIPn/RRINGn, based on the selection of T1 (1.544) or E1 (2.048) mode in the LTRCR register. Bit 3: Receiver Turns Ratio (RTR) 0 = Receive transformer turns ratio is 1:1. 1 = Receive transformer turns ratio is 2:1. This option should only be used in short-haul applications. Note: Internal impedance match is not available for this mode. Bit 2: Receiver Monitor Mode Enable (RMONEN) 0 = Disable receive monitor mode. 1 = Enable receive monitor mode. Resistive gain is added with the maximum sensitivity. The receiver sensitivity is determined by RSMS1 and RSMS0. Bits 1 and 0: Receiver Sensitivity/Monitor Gain Select (RSMS[1:0]). These bits are used to select the receiver sensitivity level and additional gain in monitoring applications. The monitor mode (RMONEN) adds resistive gain to compensate for the signal loss caused by the isolation resistors. See Table 10-20 and Table 10-21. Table 10-20. Receiver Sensitivity Selection with Monitor Mode Disabled RMONEN 0 0 0 0 RSMS[1:0] 00 01 10 11 RECEIVER MONITOR MODE GAIN (dB) 0 0 0 0 RECEIVER SENSITIVITY (MAX CABLE LOSS ALLOWED) (dB) 12 20 30 36 for T1; 43 for E1 Table 10-21. Receiver Sensitivity Selection with Monitor Mode Enabled RMONEN 1 1 1 1 RSMS[1:0] 00 01 10 11 RECEIVER MONITOR MODE GAIN (dB) 14 20 26 32 RECEIVER SENSITIVITY (MAX CABLE LOSS ALLOWED) (dB) 30 22.5 17.5 12 236 of 286 DS26518 8-Port T1/E1/J1 Transceiver 10.6 BERT Register Definitions Table 10-22. BERT Register Set ADDRESS 1100h 1101h 1102h 1103h 1104h 1105h 1106h 1107h 1108h 1109h 110Ah 110Bh 110Ch 110Dh 110Eh 110Fh NAME BAWC BRP1 BRP2 BRP3 BRP4 BC1 BC2 BBC1 BBC2 BBC3 BBC4 BEC1 BEC2 BEC3 BLSR BSIM DESCRIPTION BERT Alternating Word Count Rate Register BERT Repetitive Pattern Set Register 1 BERT Repetitive Pattern Set Register 2 BERT Repetitive Pattern Set Register 3 BERT Repetitive Pattern Set Register 4 BERT Control Register 1 BERT Control Register 2 BERT Bit Count Register 1 BERT Bit Count Register 2 BERT Bit Count Register 3 BERT Bit Count Register 4 BERT Error Count Register 1 BERT Error Count Register 2 BERT Error Count Register 3 BERT Latched Status Register BERT Status Interrupt Mask Register R/W R R/W R/W R/W R/W R/W R/W R R R R R R R R R/W Register Name: Register Description: Register Address: BAWC BERT Alternating Word Count Rate Register 1100h + (10h x (n - 1)) : where n = 1 to 8 6 ACNT6 0 5 ACNT5 0 4 ACNT4 0 3 ACNT3 0 2 ACNT2 0 1 ACNT1 0 0 ACNT0 0 Bit # Name Default 7 ACNT7 0 Bits 7 to 0: Alternating Word Count Rate Bits 7 to 0 (ACNT[7:0]). When the BERT is programmed in the alternating word mode, the words will repeat for the count loaded into this register then flip to the other word and again repeat for the number of times loaded into this register. ACNT0 is the LSB of the 8-bit alternating word count rate counter. 237 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BRP1 BERT Repetitive Pattern Set Register 1 1101h + (10h x (n - 1)) : where n = 1 to 8 6 RPAT6 0 5 RPAT5 0 4 RPAT4 0 3 RPAT3 0 2 RPAT2 0 1 RPAT1 0 0 RPAT0 0 Bit # Name Default 7 RPAT7 0 Bits 7 to 0: BERT Repetitive Pattern Set Bits 7 to 0 (RPAT[7:0]). RPAT0 is the LSB of the 32-bit repetitive pattern. Register Name: Register Description: Register Address: BRP2 BERT Repetitive Pattern Set Register 2 1102h + (10h x (n - 1)) : where n = 1 to 8 6 RPAT14 0 5 RPAT13 0 4 RPAT12 0 3 RPAT11 0 2 RPAT10 0 1 RPAT9 0 0 RPAT8 0 Bit # Name Default 7 RPAT15 0 Bits 7 to 0: BERT Repetitive Pattern Set Bits 15 to 8 (RPAT[15:8]) Register Name: Register Description: Register Address: BRP3 BERT Repetitive Pattern Set Register 3 1103h + (10h x (n - 1)) : where n = 1 to 8 6 RPAT22 0 5 RPAT21 0 4 RPAT20 0 3 RPAT19 0 2 RPAT18 0 1 RPAT17 0 0 RPAT16 0 Bit # Name Default 7 RPAT23 0 Bits 7 to 0: BERT Repetitive Pattern Set Bits 23 to 16 (RPAT[23:16]) Register Name: Register Description: Register Address: BRP4 BERT Repetitive Pattern Set Register 4 1104h + (10h x (n - 1)) : where n = 1 to 8 6 RPAT30 0 5 RPAT29 0 4 RPAT28 0 3 RPAT27 0 2 RPAT26 0 1 RPAT25 0 0 RPAT24 0 Bit # Name Default 7 RPAT31 0 Bits 7 to 0: BERT Repetitive Pattern Set Bits 31 to 24 (RPAT[31:24]). RPAT31 is the MSB of the 32-bit repetitive pattern. 238 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TC 0 BC1 BERT Control Register 1 1105h + (10h x (n - 1)) : where n = 1 to 8 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for a subsequent loads. Bit 6:Transmit Invert Data Enable (TINV) 0 = Do not invert the outgoing data stream. 1 = Invert the outgoing data stream. Bit 5:Receive Invert Data Enable (RINV). 0 = Do not invert the incoming data stream. 1 = Invert the incoming data stream. Bits 4 to 2: Pattern Select Bits 2 to 0 (PS[2:0]). These bits select data pattern used by the transmit and receive circuits. See Table 10-23. Table 10-23. BERT Pattern Select PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 PATTERN DEFINITION Pseudorandom 2E7-1. Pseudorandom 2E11-1. Pseudorandom 2E15-1. Pseudorandom Pattern QRSS. A 220 - 1 pattern with 14 consecutive zero restriction. Repetitive Pattern. Alternating Word Pattern. Modified 55 Octet (Daly) Pattern. The Daly pattern is a repeating 55 octet pattern that is byte-aligned into the active DS0 time slots. The pattern is defined in an ATIS (Alliance for Telecommunications Industry Solutions) Committee T1 Technical Report Number 25 (November 1993). Pseudorandom 2E-9-1. Bit 1: Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into the registers BBC1, BBC2, BBC3, BBC4 and BEC1, BEC2, BEC3 and clears the internal count. This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for a subsequent loads. Bit 0: Force Resynchronization (RESYNC). A low-to-high transition will force the receive BERT synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization. 239 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BC2 BERT Control Register 2 1106h + (10h x (n - 1)) : where n = 1 to 8 6 EIB1 0 5 EIB0 0 4 SBE 0 3 RPL3 0 2 RPL2 0 1 RPL1 0 0 RPL0 0 Bit # Name Default 7 EIB2 0 Bits 7 to 5: Error Insert Bits 2 to 0 (EIB[2:0]). Will automatically insert bit errors at the prescribed rate into the generated data pattern. Can be used for verifying error detection features. See Table 10-24. Table 10-24. BERT Error Insertion Rate EIB2 0 0 0 0 1 1 1 1 EIB1 0 0 1 1 0 0 1 1 EIB0 0 1 0 1 0 1 0 1 ERROR RATE INSERTED No errors automatically inserted 10E-1 10E-2 10E-3 10E-4 10E-5 10E-6 10E-7 Bit 4: Single Bit Error Insert (SBE). A low-to-high transition will create a single bit error. Must be cleared and set again for a subsequent bit error to be inserted. Bits 3 to 0: Repetitive Pattern Length Select 3 to 0 (RPL[3:0]). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns fewer than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101). See Table 10-25. Table 10-25. BERT Repetitive Pattern Length Select LENGTH (BITS) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RPL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RPL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RPL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RPL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 240 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BBC1 BERT Bit Count Register 1 1107h + (10h x (n - 1)) : where n = 1 to 8 6 BBC6 0 5 BBC5 0 4 BBC4 0 3 BBC3 0 2 BBC2 0 1 BBC1 0 0 BBC0 0 Bit # Name Default 7 BBC7 0 Bits 7 to 0: BERT Bit Counter Bits 7 to 0 (BBC[7:0]). BBC0 is the LSB of the 32-bit counter. Register Name: Register Description: Register Address: BBC2 BERT Bit Count Register 2 1108h + (10h x (n - 1)) : where n = 1 to 8 6 BBC14 0 5 BBC13 0 4 BBC12 0 3 BBC11 0 2 BBC10 0 1 BBC9 0 0 BBC8 0 Bit # Name Default 7 BBC15 0 Bits 7 to 0: BERT Bit Counter Bits 15 to 8 (BBC[15:8]). Register Name: Register Description: Register Address: BBC3 BERT Bit Count Register 3 1109h + (10h x (n - 1)) : where n = 1 to 8 6 BBC22 0 5 BBC21 0 4 BBC20 0 3 BBC19 0 2 BBC18 0 1 BBC17 0 0 BBC16 0 Bit # Name Default 7 BBC23 0 Bits 7 to 0: BERT Bit Counter Bits 23 to 16 (BBC[23:16]). Register Name: Register Description: Register Address: BBC4 BERT Bit Count Register 4 110Ah + (10h x (n - 1)) : where n = 1 to 8 6 BBC30 0 5 BBC29 0 4 BBC28 0 3 BBC27 0 2 BBC26 0 1 BBC25 0 0 BBC24 0 Bit # Name Default 7 BBC31 0 Bits 7 to 0: BERT Bit Counter Bits 31 to 24 (BBC[31:24]). BBC31 is the MSB of the 32-bit counter. 241 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BEC1 BERT Error Count Register 1 110Bh + (10h x (n - 1)) : where n = 1 to 8 6 EC6 0 5 EC5 0 4 EC4 0 3 EC3 0 2 EC2 0 1 EC1 0 0 EC0 0 Bit # Name Default 7 EC7 0 Bits 7 to 0: Error Counter Bits 7 to 0 (EC[7:0]). EC0 is the LSB of the 24-bit counter. Register Name: Register Description: Register Address: BEC2 BERT Error Count Register 2 110Ch + (10h x (n - 1)) : where n = 1 to 8 6 EC14 0 5 EC13 0 4 EC12 0 3 EC11 0 2 EC10 0 1 EC9 0 0 EC8 0 Bit # Name Default 7 EC15 0 Bits 7 to 0: Error Counter Bits 15 to 8 (EC[15:8]) Register Name: Register Description: Register Address: BEC3 BERT Error Count Register 3 110Dh + (10h x (n - 1)) : where n = 1 to 8 6 EC22 0 5 EC21 0 4 EC20 0 3 EC19 0 2 EC18 0 1 EC17 0 0 EC16 0 Bit # Name Default 7 EC23 0 Bits 7 to 0: Error Counter Bits 23 to 16 (EC[23:16]). EC23 is the MSB of the 24-bit counter. 242 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BLSR BERT Latched Status Register 110Eh + (10h x (n - 1)) : where n = 1 to 8 6 BBED 0 5 BBCO 0 4 BECO 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Bit # Name Default 7 -- 0 Note: All bits in this register are latched and can create interrupts. Bit 6: BERT Bit Error Detected Event (BBED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors. Bit 5: BERT Bit Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC) overflows. Bit 4: BERT Error Counter Overflow Event (BECO). A latched bit that is set when the 24-bit BERT error counter (BEC) overflows. Bit 3: BERT Receive All-Ones Condition (BRA1). A latched bit that is set when 32 consecutive ones are received. Bit 2: BERT Receive All-Zeros Condition (BRA0). A latched bit that is set when 32 consecutive zeros are received. Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS). A latched bit that is set whenever the receive BERT begins searching for a pattern. Bit 0: BERT in Synchronization Condition (BSYNC). Will be set when the incoming pattern matches for 32 consecutive bit positions. 243 of 286 DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BSIM BERT Status Interrupt Mask Register 110Fh + (10h x (n - 1)) : where n = 1 to 8 6 BBED 0 5 BBCO 0 4 BECO 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Bit # Name Default 7 -- 0 Bit 6: BERT Bit Error Detected Event (BBED) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: BERT Bit Counter Overflow Event (BBCO) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: BERT Error Counter Overflow Event (BECO) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: BERT Receive All Ones Condition (BRA1) 0 = Interrupt masked. 1 = Interrupt enabled--interrupts on rising and falling edges. Bit 2: BERT Receive All Zeros Condition (BRA0) 0 = Interrupt masked. 1 = Interrupt enabled--interrupts on rising and falling edges. Bit 1: BERT Receive Loss Of Synchronization Condition (BRLOS) 0 = Interrupt masked. 1 = Interrupt enabled--interrupts on rising and falling edges. Bit 0: BERT in Synchronization Condition (BSYNC) 0 = Interrupt masked. 1 = Interrupt enabled--interrupts on rising and falling edges. 244 of 286 DS26518 8-Port T1/E1/J1 Transceiver 11. 11.1 FUNCTIONAL TIMING T1 Receiver Functional Timing Diagrams Figure 11-1. T1 Receive-Side D4 Timing FRAME# RFSYNCn RSYNCn1 RSYNCn2 RSYNCn3 NOTE 1: RSYNCn IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RIOCR.1 = 0). NOTE 2: RSYNCn IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RIOCR.1 = 1). NOTE 3: RSYNCn IN THE MULTIFRAME MODE (RIOCR.0 = 1). 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 Figure 11-2. T1 Receive-Side ESF Timing FRAME# RSYNCn1 RFSYNCn RSYNCn2 RSYNCn3 NOTE 1: RSYNCn IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RIOCR.1 = 0). NOTE 2: RSYNCn IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RIOCR.1 = 1). NOTE 3: RSYNCn IN THE MULTIFRAME MODE (RIOCR.0 = 1). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 245 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) RCLKn CHANNEL 23 CHANNEL 24 LSB MSB LSB CHANNEL 1 RSERn RSYNCn RFSYNCn RSIGn RCHCLKn RCHBLKn1 F MSB CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A NOTE 1: RCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) RSYSCLKn CHANNEL 23 CHANNEL 24 LSB MSB LSB CHANNEL 1 RSERn RSYNCn1 RMSYNCn RSYNCn2 RSIGn RCHCLKn RCHBLK3 F MSB CHANNEL 23 A B C/A D/B CHANNEL 24 B C/A D/B A CHANNEL 1 A NOTE 1: RSYNCn IS IN THE OUTPUT MODE (RIOCR.2 = 0). NOTE 2: RSYNCn IS IN THE INPUT MODE (RIOCR.2 = 1). NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. 246 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSYSCLKn CHANNEL 31 CHANNEL 32 LSB MSB LSB CHANNEL 1 RSERn 1 RSYNCn2 RMSYNCn RSYNCn3 RSIGn RCHCLKn RCHBLKn4 NOTE 1: RSERn DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO ONE. NOTE 2: RSYNCn IS IN THE OUTPUT MODE (RIOCR.2 = 0). NOTE 3: RSYNCn IS IN THE INPUT MODE (RIOCR.2 = 1). NOTE 4: RCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 1. NOTE 5: THE F-BIT POSITION IS PASSED THROUGH THE RECEIVE-SIDE ELASTIC STORE. A CHANNEL 31 B C/A D/B A CHANNEL 32 B C/A D/B CHANNEL 1 247 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-6. T1 Receive-Side Interleave Bus Operation--BYTE Mode RSYNCn RSERn1 RSIGn1 RSERn2 RSIGn2 FR1 CH32 FR1 CH32 FR0 CH1 FR0 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR2 CH1 FR2 CH1 FR3 CH1 FR3 CH1 FR0 CH2 FR0 CH2 FR0 CH2 FR0 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR2 CH2 FR2 CH2 FR3 CH2 FR3 CH2 FR2 CH32 FR3 CH32 FR0 CH1 FR2 CH32 FR3 CH32 FR0 CH1 BIT DETAIL RSYSCLKn RSYNCn3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB FRAMER 1, CHANNEL 1 LSB RSERn RSIGn A B C LSB MSB FRAMER 3, CHANNEL 32 D FRAMER 0, CHANNEL 1 A B C D FRAMER 1, CHANNEL 1 A B C D NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: RSYNCn IS IN THE INPUT MODE (RIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, RCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, RCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER'S ACTIVE PERIOD. 248 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-7. T1 Receive-Side Interleave Bus Operation--FRAME Mode RSYNCn RSERn1 FR1 CH1-32 RSIGn1 RSERn2 RSIGn2 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL RSYSCLKn RSYNCn FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB FRAMER 0, CHANNEL 2 LSB RSERn RSIGn A B LSB MSB FRAMER 3, CHANNEL 32 C/A D/B FRAMER 0, CHANNEL 1 A B C/A D/B FRAMER 0, CHANNEL 2 A B C/A D/B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: RSYNCn IS IN THE INPUT MODE (RIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, RCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, RCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER'S ACTIVE PERIOD. Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit RCLKn RCHCLKn RSYNCn RSERn LSB F-BIT MSB 249 of 286 DS26518 8-Port T1/E1/J1 Transceiver 11.2 T1 Transmitter Functional Timing Diagrams Figure 11-9. T1 Transmit-Side D4 Timing FRAME# TSYNCn1 TSSYNCIOn TSYNCn2 TSYNCn3 NOTE 1: TSYNCn IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0). NOTE 2: TSYNCn IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1). NOTE 3: TSYNCn IN THE MULTIFRAME MODE (TIOCR.0 = 1). 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 Figure 11-10. T1 Transmit-Side ESF Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 TSYNCn1 TSSYNCIOn TSYNCn2 TSYNCn3 NOTE 1: TSYNCn IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0). NOTE 2: TSYNCn IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1). NOTE 3: TSYNCn IN THE MULTIFRAME MODE (TIOCR.0 = 1). 250 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) TCLKn CHANNEL 1 CHANNEL 2 LSB MSB LSB MSB TSERn TSYNCn1 TSYNCn2 LSB F MSB CHANNEL 1 CHANNEL 2 C/A D/B A B C/A D/B TSIGn TCHCLKn TCHBLKn3 D/B A B NOTE 1: TSYNCn IS IN THE OUTPUT MODE (TIOCR.2 = 1). NOTE 2: TSYNCn IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 3: TCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 2. Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) TSYSCLKn CHANNEL 23 CHANNEL 24 LSB MSB LSB F MSB CHANNEL 1 TSERn TSSYNCIOn CHANNEL 23 CHANNEL 24 C/A D/B A B C/A D/B CHANNEL 1 A TSIGn TCHCLKn TCHBLKn1 A B NOTE 1: TCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 24. 251 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) TSYSCLKn CHANNEL 31 CHANNEL 32 LSB MSB LSB F3 CHANNEL 1 TSERn1 TSSYNCIOn CHANNEL 31 CHANNEL 32 C/A D/B A B C/A D/B CHANNEL 1 A TSIGn TCHCLKn TCHBLKn2 A B NOTE 1: TSERn DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED. NOTE 2: TCHBLKn IS PROGRAMMED TO BLOCK CHANNELS 31 AND 1. NOTE 3: THE F-BIT POSITION FOR THE T1 FRAME IS SAMPLED AND PASSED THROUGH THE TRANSMIT-SIDE ELASTIC STORE INTO THE MSB BIT POSITION OF CHANNEL 1. (NORMALLY THE TRANSMIT-SIDE FORMATTER OVERWRITES THE F-BIT POSITION UNLESS THE FORMATTER IS PROGRAMMED TO PASS THROUGH THE F-BIT POSITION). 252 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-14. T1 Transmit-Side Interleave Bus Operation--BYTE Mode TSSYNCIOn TSERn1 TSIGn1 TSERn2 TSIGn2 FR1 CH32 FR1 CH32 FR2 CH32 FR2 CH32 FR3 CH32 FR3 CH32 FR0 CH1 FR0 CH1 FR0 CH1 FR0 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR2 CH1 FR2 CH1 FR3 CH1 FR3 CH1 FR0 CH2 FR0 CH2 FR0 CH2 FR0 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR2 CH2 FR2 CH2 FR3 CH2 FR3 CH2 BIT DETAIL TSYSCLKn TSSYNCIOn3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB LSB MSB FRAMER 1, CHANNEL 1 LSB TSERn TSIGn A B C/A FRAMER 3, CHANNEL 32 D/B FRAMER 0, CHANNEL 1 A B C/A D/B FRAMER 1, CHANNEL 1 A B C/A D/B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: TSSYNCIOn IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, TCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, TCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER'S ACTIVE PERIOD. 253 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-15. T1 Transmit-Side Interleave Bus Operation--FRAME Mode TSSYNCIOn TSERn1 TSIGn1 TSERn2 TSIGn2 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL TSYSCLKn TSSYNCIOn3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB FRAMER 0, CHANNEL 2 LSB TSERn TSIGn A B LSB MSB FRAMER 3, CHANNEL 32 C/A D/B FRAMER 0, CHANNEL 1 A B C/A D/B FRAMER 0, CHANNEL 2 A B C/A D/B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: TSSYNCIOn IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, TCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, TCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER'S ACTIVE PERIOD. Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit TCLKn TCHCLKn TSYNCn TSERn LSB MSB 254 of 286 DS26518 8-Port T1/E1/J1 Transceiver 11.3 E1 Receiver Functional Timing Diagrams Figure 11-17. E1 Receive-Side Timing FRAME# RFSYNCn RSYNCn1 RSYNCn2 NOTE 1: RSYNCn IN FRAME MODE (RIOCR.0 = 0). NOTE 2: RSYNCn IN MULTIFRAME MODE (RIOCR.0 = 1). NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) RCLKn CHANNEL 32 RSERn RSYNCn RFSYNCn RSIGn RCHCLKn 1 LSB Si 1 A CHANNEL 1 Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 2 CHANNEL 32 C A B CHANNEL 1 D Note 3 CHANNEL 2 A B RCHBLKn1 NOTE 1: RCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 1. NOTE 2: SHOWN IS AN RNAF FRAME BOUNDARY. NOTE 3. RSIGn NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1. 255 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) RSYSCLKn CHANNEL 23/31 CHANNEL 24/32 LSB CHANNEL 1/2 RSERn 1 LSB MSB F MSB RSYNCn2 RMSYNCn RSYNCn3 RCHCLKn RCHBLKn4 NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ONE). NOTE 2: RSYNCn IN THE OUTPUT MODE (RIOCR.2 = 0). NOTE 3: RSYNCn IN THE INPUT MODE (RIOCR.2 = 1). NOTE 4: RCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSYSCLKn CHANNEL 31 CHANNEL 32 LSB MSB LSB MSB CHANNEL 1 RSERn RSYNCn1 RMSYNCn RSYNCn2 RSIGn RCHCLKn RCHBLKn3 A CHANNEL 31 C B D A CHANNEL 32 C B D CHANNEL 1 Note 4 NOTE 1: RSYNCn IN THE OUTPUT MODE (RIOCR.2 = 0). NOTE 2: RSYNCn IN THE INPUT MODE (RIOCR.2 = 1). NOTE 3: RCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 1. NOTE 4: RSIGn NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1. 256 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-21. E1 Receive-Side Interleave Bus Operation--BYTE Mode RSYNCn RSERn1 RSIGn1 RSERn2 RSIGn2 FR1 CH32 FR1 CH32 FR0 CH1 FR0 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR2 CH1 FR2 CH1 FR3 CH1 FR3 CH1 FR0 CH2 FR0 CH2 FR0 CH2 FR0 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR2 CH2 FR2 CH2 FR3 CH2 FR3 CH2 FR2 CH32 FR3 CH32 FR0 CH1 FR2 CH32 FR3 CH32 FR0 CH1 BIT DETAIL RSYSCLKn RSYNCn3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB FRAMER 1, CHANNEL 1 LSB RSERn RSIGn A B C LSB MSB FRAMER 3, CHANNEL 32 D FRAMER 0, CHANNEL 1 A B C D FRAMER 1, CHANNEL 1 A B C D NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: RSYNCn IS IN THE INPUT MODE (RIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, RCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, RCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER'S ACTIVE PERIOD. 257 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-22. E1 Receive-Side Interleave Bus Operation--FRAME Mode RSYNCn RSERn1 FR1 CH1-32 RSIGn1 RSERn2 RSIGn2 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL RSYSCLKn RSYNCn3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB FRAMER 0, CHANNEL 2 LSB RSERn RSIGn A B LSB MSB FRAMER 3, CHANNEL 32 C/A D/B FRAMER 0, CHANNEL 1 A B C/A D/B FRAMER 0, CHANNEL 2 A B C/A D/B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: RSYNC IS IN THE INPUT MODE (RIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, RCHCLK CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, RCHBLK CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER'S ACTIVE PERIOD. Figure 11-23. E1 Receive-Side RCHCLKn Gapped Mode During Channel 1 RCLKn RSYNCn RCHCLKn RSERn LSB F F F F F F F F MSB 258 of 286 DS26518 8-Port T1/E1/J1 Transceiver 11.4 E1 Transmitter Functional Timing Diagrams Figure 11-24. E1 Transmit-Side Timing FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 TSYNCn1 TSSYNCIOn TSYNCn2 NOTE 1: TSYNCn IN FRAME MODE (TIOCR.0 = 0). NOTE 2: TSYNCn IN MULTIFRAME MODE (TIOCR.0 = 1). NOTE 3: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC-4 MF BEGIN WITH THE TAF FRAME. Figure 11-25. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) TCLKn CHANNEL 1 CHANNEL 2 LSB MSB TSERn TSYNCn1 TSYNCn2 LSB Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 1 CHANNEL 2 A B C D TSIGn TCHCLKn TCHBLKn3 D NOTE 1: TSYNCn IN THE OUTPUT MODE (TIOCR.2 = 1). NOTE 2: TSYNCn IN THE INPUT MODE (TIOCR.2 = 0). NOTE 3: TCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 2. NOTE 4: THE SIGNALING DATA AT TSIGn DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT FORMATTER WITH THE CAS MF ALIGNMENT NIBBLE (0000). NOTE 5: SHOWN IS A TNAF FRAME BOUNDARY. 259 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-26. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) TSYSCLKn CHANNEL 23 CHANNEL 24 LSB MSB LSB F MSB CHANNEL 1 TSERn 1 TSSYNCIOn TCHCLKn TCHBLKn2 NOTE 1: THE F-BIT POSITION IN THE TSERn DATA IS IGNORED. NOTE 2: TCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 11-27. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) TSYSCLKn CHANNEL 31 CHANNEL 32 LSB MSB LSB MSB CHANNEL 1 TSERn TSYNCn1 TSIGn TCHCLKn TCHBLKn2 A CHANNEL 31 C B D A CHANNEL 32 C B D CHANNEL 1 NOTE 1: TSYNCn IN THE INPUT MODE (TIOCR.2 = 0). NOTE 2: TCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 1. 260 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-28. E1 Transmit-Side Interleave Bus Operation--BYTE Mode TSSYNCIOn TSERn1 TSIGn1 TSERn2 TSIGn2 FR1 CH32 FR1 CH32 FR2 CH32 FR2 CH32 FR3 CH32 FR3 CH32 FR0 CH1 FR0 CH1 FR0 CH1 FR0 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR1 CH1 FR2 CH1 FR2 CH1 FR3 CH1 FR3 CH1 FR0 CH2 FR0 CH2 FR0 CH2 FR0 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR1 CH2 FR2 CH2 FR2 CH2 FR3 CH2 FR3 CH2 BIT DETAIL TSYSCLKn TSSYNCIOn3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB LSB MSB FRAMER 1, CHANNEL 1 LSB TSERn TSIGn A B C/A FRAMER 3, CHANNEL 32 D/B FRAMER 0, CHANNEL 1 A B C/A D/B FRAMER 1, CHANNEL 1 A B C/A D/B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: TSSYNCIOn IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, TCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, TCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER'S ACTIVE PERIOD. 261 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-29. E1 Transmit-Side Interleave Bus Operation--FRAME Mode TSSYNCIOn TSERn1 TSIGn1 TSERn2 TSIGn2 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL TSYSCLKn TSSYNCIOn3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1 LSB MSB FRAMER 0, CHANNEL 2 LSB TSERn TSIGn A B LSB MSB FRAMER 3, CHANNEL 32 C/A D/B FRAMER 0, CHANNEL 1 A B C/A D/B FRAMER 0, CHANNEL 2 A B C/A D/B NOTE 1: 4.096MHz BUS CONFIGURATION. NOTE 2: 8.192MHz BUS CONFIGURATION. NOTE 3: TSSYNCIOn IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 4: THOUGH NOT SHOWN, TCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD. NOTE 5: THOUGH NOT SHOWN, TCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER'S ACTIVE PERIOD. 262 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 11-30. E1 G.802 Timing TS# 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 23 24 25 2627 28 29 30 31 0 1 2 RSYNCn TSYNCn RCHCLKn TCHCLKn RCHBLKn TCHBLKn RCLKn/RSYSCLKn TCLKn/TSYSCLKn CHANNEL 25 CHANNEL 26 LSB MSB RSERn/TSERn RCHCLKn/TCHCLKn RCHBLKn/TCHBLKn NOTE: RCHBLKn OR TCHBLKn PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15, 17 THROUGH 25, AND BIT 1 OF TIME SLOT 26. Figure 11-31. E1 Transmit-Side TCHCLKn Gapped Mode During Channel 1 TCLKn TSYNCn TCHCLKn TSERn LSB MSB 263 of 286 DS26518 8-Port T1/E1/J1 Transceiver 12. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD)....................................................-0.3V to +5.5V Supply Voltage (VDD) Range with Respect to VSS....................................................................-0.3V to +3.63V Operating Temperature Range Commercial (DS26518G)..........................................................................................0C to +70C Industrial (DS26518GN)..........................................................................................-40C to +85C Storage Temperature Range.............................................................................................-55C to +125C Soldering Temperature...................................................................See IPC/JEDEC J-STD-020 Specification This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Table 12-1. Recommended DC Operating Conditions (TA = -40C to +85C for DS26518GN.) PARAMETER Logic 1 Logic 0 I/O Supply Core Supply SYMBOL VIH VIL VDD VDD-CORE CONDITIONS MIN 2.0 -0.3 3.135 1.71 3.3 1.8 TYP MAX 5.5 +0.8 3.465 1.89 UNITS V V V V Table 12-2. Capacitance (TA = +25C) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT CONDITIONS MIN TYP 7 7 MAX UNITS pF pF Table 12-3. Recommended DC Operating Conditions (VDD = 3.135V to 3.465V, TA = -40C to +85C for DS26518GN.) PARAMETER 3.3V Supply Current 1.8V Core Supply Current Input Leakage Pullup Pin Input Leakage Pulldown Pin Input Leakage Tri-State Output Leakage Output Voltage (IOH = -4mA) Output Voltage (IOL = +4mA) Note 1: Note 2: Note 3: SYMBOL IDD IDD-CORE IIL IILP IILP IOL VOH VOL CONDITIONS (Notes 1, 2) (Notes 1, 2) MIN TYP 300 75 MAX 450 100 +10.0 +10.0 +85.0 +10.0 UNITS mA mA A A A A V -10.0 (Note 3) (Note 3) -85.0 -10.0 -10.0 2.4 0.4 V RCLK1-n = TCLK1-n = 2.048MHz, digital outputs without load. Max power consumed is measured with all ports transmitting an all-ones data pattern with a transmitter load of 100. Pullup/pulldown pins include SPI_SEL, TSYSCLK[2:8], RSYSCLK[2:8], DIGIOEN, JTRST, JTMS, and JTDI. 264 of 286 DS26518 8-Port T1/E1/J1 Transceiver 12.1 Thermal Characteristics Table 12-4. Thermal Characteristics PARAMETER Ambient Temperature Junction Temperature Theta-JA (JA) in Still Air for 256-Pin TE-CSBGA Note 1: Note 2: CONDITIONS (Note 1) MIN -40 TYP MAX +85 +125 UNITS C C C/W (Note 2) +17.5 The package is mounted on a four-layer JEDEC standard test board. Theta-JA (JA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board. 12.2 Line Interface Characteristics Table 12-5. Transmitter Characteristics PARAMETER SYMBOL CONDITIONS E1 75 E1 120 T1 100 J1 110 (Note 1) MIN 2.13 2.70 2.40 2.40 -0.3 TYP 2.37 3.00 3.00 3.00 MAX 2.61 3.30 3.60 3.60 +0.3 UNITS Output Mark Amplitude Vm V Output Zero Amplitude Transmit Amplitude Variation with Supply Vs V -1 +1 % Table 12-6. Receiver Characteristics PARAMETER Cable Attenuation Allowable Zeros Before Loss (Note 1) Allowable Ones Before Loss (Note 2) Note 1: Note 2: SYMBOL Attn CONDITIONS MIN TYP MAX 43 UNITS dB 192 192 2048 24 192 192 192 zeros for T1 and T1.231 Specification Compliance. 192 zeros for E1 and G.775 Specification Compliance. 2048 zeros for ETS 300 233 compliance. 24 ones in 192-bit period for T1.231; 192 ones for G.775; 192 ones for ETS 300 233. 265 of 286 DS26518 8-Port T1/E1/J1 Transceiver 13. AC TIMING CHARACTERISTICS Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus signals. 13.1 Microprocessor Bus AC Characteristics 13.1.1 SPI Bus Mode Table 13-1. SPI Bus Mode Timing (See Figure 13-1.) SYMBOL (Note 1) CHARACTERISTIC (Note 2) Operating Frequency Slave t1 t2 t3 t4, t5 t6 t7 t8 t9 t10 Note 1: Note 2: Note 3: Note 4: SYMBOL MIN MAX 5 UNITS MHz ns ns ns ns ns ns fBUS(S) tCYC(S) tLEAD(S) tLAG(S) tCLKH(S) tSU(S) tH(S) tDIS(S) tV(S) tHD(S) 5 200 15 15 80 5 15 Cycle Time: Slave Enable Lead Time Enable Lag Time Clock (CLK) Duty Cycle Slave (t4/t1 or t5/t1) Data Setup Time (Inputs) Slave Data Hold Time (Inputs) Slave Disable Time, Slave (Note 3) Data Valid Time, After Enable Edge Slave (Note 4) Data Hold Time, Outputs, After Enable Edge Slave Symbols refer to dimensions in Figure 13-1. 100pF load on all SPI pins. Hold time to high-impedance state. With 100pF on all SPI pins. 25 40 ns ns ns 266 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 13-1. SPI Interface Timing Diagram CSB INPUT t2 t1 t3 SPI_SCLK t4 t5 SPI_SCLK1 t8 MOSI INPUT t6 t7 SLAVE MSB t9 BITS 6:1 t10 SLAVE LSB NOTE 2 MISO OUTPUT MSB BIT 14 BITS 13:0 NOTE 1: CLOCK EDGE REFERENCE TO DATA CONTROLLED BY CPHA AND CPOL SETTINGS. SEE THE FUNCTIONAL TIMING DIAGRAMS. NOTE 2: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST RECEIVED. 267 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 13-2. AC Characteristics--Microprocessor Bus Timing (VDD = 3.3V 5%, TA = 0C to +70C for DS26518G; VDD = 3.3V 5%, TA = -40C to +85C for DS26518GN.) (See Figure 13-2, Figure 13-3, Figure 13-4, and Figure 13-5.) PARAMETER Setup Time for A[12:0] Valid to CSB Active Setup Time for CSB Active to Either RDB, or WRB Active Delay Time from Either RDB or DSB Active to D[7:0] Valid Hold Time from Either RDB or WRB Inactive to CSB Inactive Hold Time from CSB or RDB or DSB Inactive to D[7:0] Tri-State Wait Time from WRB Active to Latch Data Data Setup Time to WRB Inactive Data Hold Time from WRB Inactive Address Hold from WRB Inactive Write Access to Subsequent Write/Read Access Delay Time Note 1: SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 CONDITIONS MIN 0 0 TYP MAX UNITS ns ns (Note 1) 0 5 40 10 2 0 (Note 1) 30 175 ns ns 20 ns ns ns ns ns ns If supplying a 1.544MHz MCLK, the FREQSEL bit must be set to meet this timing. 268 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 13-2. Intel Bus Read Timing (BTS = 0) t9 A[12:0] D[7:0] WRB Address Valid Data Valid t5 t1 CSB t2 t3 t4 t10 RDB Figure 13-3. Intel Bus Write Timing (BTS = 0) t9 A[12:0] D[7:0] Address Valid t7 t8 RDB t1 CSB t2 t6 t4 t10 WRB 269 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 13-4. Motorola Bus Read Timing (BTS = 1) t9 A[12:0] D[7:0] RWB Address Valid Data Valid t5 t1 CSB t2 t3 t4 t10 DSB Figure 13-5 Motorola Bus Write Timing (BTS = 1) t9 A[12:0] D[7:0] Address Valid t7 t8 RWB t1 CSB t2 t6 t4 t10 DSB 270 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 13-3. Receiver AC Characteristics (VDD = 3.3V 5%, TA = 0C to +70C for DS26518G; TA = -40C to +85C for DS26518GN.) (See Figure 13-6, Figure 13-7, and Figure 13-8.) PARAMETER RCLKn Period RCLKn Pulse Width RSYSCLKn Period RSYSCLKn Pulse Width RSYNCn Setup to RSYSCLKn Falling RSYNCn Pulse Width Delay RCLKn to RSERn, RSIGn Valid Delay RCLKn to RCHCLKn, RSYNCn, RCHBLKn, RFSYNCn Delay RSYSCLKn to RSERn, RSIGn Valid Delay RSYSCLKn to RCHCLKn, RCHBLKn, RMSYNCn, RSYNCn Note 1: Note 2: Note 3: Note 4: SYMBOL tCP tCH tCL tSP tSH tSL tSU tPW tD1 tD2 tD3 tD4 CONDITIONS (Note 1) (Note 2) MIN TYP 648 488 MAX UNITS ns ns ns ns ns ns (Note 3) (Note 4) 125 125 60 60 30 30 10 50 10 20 20 20 ns ns ns ns T1 Mode. E1 Mode. RSYSCLKn = 1.544MHz. RSYSCLKn = 2.048MHz. 271 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 13-6. Receive Framer Timing--Backplane (T1 Mode) RCLKn t D1 RSERn/RSIGn t D2 F-BIT RCHCLKn t D2 RCHBLKn t D2 RFSYNCn/RMSYNCn t D2 RSYNCn1 NOTE 1: RSYNCn IS IN THE OUTPUT MODE. NOTE 2: NO RELATIONSHIP BETWEEN RCHCLKn AND RCHBLKn AND OTHER SIGNALS IS IMPLIED. 272 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 13-7. Receive-Side Timing--Elastic Store Enabled (T1 Mode) t SL t SH RSYSCLKn t D3 t SP RSERn/RSIGn t D4 SEE NOTE 3 RCHCLKn t D4 RCHBLKn t D4 RMSYNCn t D4 1 RSYNCn t HD t SU RSYNCn2 NOTE 1: RSYNCn IS IN THE OUTPUT MODE. NOTE 2: RSYNCn IS IN THE INPUT MODE. NOTE 3: F-BIT WHEN RIOCR.4 = 0, MSB OF TS0 WHEN RIOCR.4 = 1. Figure 13-8. Receive Framer Timing--Line Side t CL RCLKn t SU RTIPn, RRINGn t HD tCP t CH 273 of 286 DS26518 8-Port T1/E1/J1 Transceiver Table 13-4. Transmit AC Characteristics (VDD = 3.3V 5%, TA = 0C to +70C for DS26518G; TA = -40C to +85C for DS26518GN.) (See Figure 13-9, Figure 13-10, and Figure 13-11.) PARAMETER TCLKn Period TCLKn Pulse Width TSYSCLKn Period TSYSCLKn Pulse Width TSYNCn or TSSYNCIOn Setup to TCLKn or TSYSCLKn Falling TSYNCn or TSSYNCIOn Pulse Width TSSYNCIOn Pulse Width (Notes 6, 7) TSERn, TSIGn Setup to TCLKn, TSYSCLKn Falling TSERn, TSIGn Hold from TCLKn, TSYSCLKn Falling Delay TCLKn to TCHBLKn, TCHCLKn, TSYNCn Delay TSYSCLKn to TCHCLKn, TCHBLKn Delay BPCLK1 to TSSYNCIOn (Note 6) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: SYMBOL tCP tCH tCL tSP tSH tSL tSU tPW tPW CONDITIONS (Note 1) (Note 2) MIN TYP 648 488 MAX UNITS ns ns ns ns ns ns (Note 3) (Note 4) 125 125 60 60 30 30 10 (Note 5) 50 488 244 122 61 10 10 20 20 5 ns tSU tHD tD2 tD3 tD5 ns ns ns ns ns T1 Mode. E1 Mode. RSYSCLKn = 1.544MHz. RSYSCLKn = 2.048MHz. TSSYNCIOn configured as an input (GTCR3.1 = 0). TSSYNCIOn configured as an output (GTCR3.1 = 1). Varies depending on the frequency of BPCLK1. 274 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 13-9. Transmit Formatter Timing--Backplane t CP t CL TCLKn t D1 TESO t SU TSERn/TSIGn t D2 TCHCLKn t D2 t D2 TSYNCn1 t SU TSYNCn2 NOTE 1: TSYNCn IS IN THE OUTPUT MODE. NOTE 2: TSYNCn IS IN THE INPUT MODE. NOTE 3: TSERn IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED. NOTE 4: TCHCLKn AND TCHBLKn ARE SYNCHRONOUS WITH TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED. NOTE 5: NO RELATIONSHIP BETWEEN TCHCLKn AND TCHBLKn AND THE OTHER SIGNALS IS IMPLIED. t CH t HD TCHBLKn t HD 275 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 13-10. Transmit Formatter Timing--Elastic Store Enabled t SP t SL TSYSCLKn t SU TSERn t D3 TCHCLKn t D3 TCHBLKn t SU TSSYNCIOn NOTE 1: TSERn IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLKn WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. NOTE 2: TCHCLKn AND TCHBLKn ARE SYNCHRONOUS WITH TSYSCLKn WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. t SH t HD t HD Figure 13-11. BPCLK1 Timing BPCLK1 TSSYNCIOn1 t D5 NOTE 1: TSSYNCIOn IS CONFIGURED AS AN OUTPUT (GTCR3.TSSYNCIOSEL = 1). 276 of 286 DS26518 8-Port T1/E1/J1 Transceiver 13.2 JTAG Interface Timing Table 13-5. JTAG Interface Timing (VDD = 3.3V 5%, TA = 0C to +70C for DS26518G; TA = -40C to +85C for DS26518GN.) (See Figure 13-12.) PARAMETER JTCLK Clock Period JTCLK Clock High:Low Time JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO High-Impedance Delay JTRST Width Low Time Note 1: SYMBOL t1 t2:t3 t4 t5 t6 t7 t8 CONDITIONS MIN TYP 1000 MAX UNITS ns ns ns ns (Note 1) 50 5 2 2 2 100 500 50 50 ns ns ns Clock can be stopped high or low. Figure 13-12. JTAG Interface Timing Diagram t1 t2 JTCLK t3 t4 JTDI, JTMS, JTRST t5 t6 t7 JTD0 JTRST t8 277 of 286 DS26518 8-Port T1/E1/J1 Transceiver 14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT The DS26518 IEEE 1149.1 design supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Table 14-1. The DS26518 contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) Bypass Register TAP Controller Boundary Scan Register Instruction Register Device Identification Register The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions for details. Figure 14-1. JTAG Functional Block Diagram BOUNDRY SCAN REGISTER IDENTIFICATION REGISTER MUX BYPASS REGISTER INSTRUCTION REGISTER TEST ACCESS PORT CONTROLLER VDD 10k SELECT OUTPUT ENABLE VDD 10k VDD 10k JTDI JTMS JTCLK JTRST JTDO 278 of 286 DS26518 8-Port T1/E1/J1 Transceiver 14.1 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 14-2. 14.1.1 Test-Logic-Reset Upon power-up, the TAP Controller will be in the Test-Logic-Reset state. The instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. 14.1.2 Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests. The Instruction Register and test registers will remain idle. 14.1.3 Select-DR-Scan All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR-Scan state. 14.1.4 Capture-DR Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test Register remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is LOW or it goes to the Exit1-DR state if JTMS is HIGH. 14.1.5 Shift-DR The test data register selected by the current instruction is connected between JTDI and JTDO and will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it maintains its previous state. 14.1.6 Exit1-DR While in this state, a rising edge on JTCLK puts the controller in the Update-DR state, which terminates the scanning process if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-DR state. 14.1.7 Pause-DR Shifting of the test registers is halted while in this state. All test registers selected by the current instruction retain their previous state. The controller remains in this state while JTMS is LOW. A rising edge on JTCLK with JTMS HIGH puts the controller in the Exit2-DR state. 14.1.8 Exit2-DR A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the Update-DR state and terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the Shift-DR state. 14.1.9 Update-DR A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. 14.1.10 Select-IR-Scan All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence 279 of 286 DS26518 8-Port T1/E1/J1 Transceiver for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-LogicReset state. 14.1.11 Capture-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the Exit1IR state. If JTMS is LOW on the rising edge of JTCLK, the controller enters the Shift-IR state. 14.1.12 Shift-IR In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all test registers, remains at their previous states. A rising edge on JTCLK with JTMS HIGH moves the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS LOW keeps the controller in the Shift-IR state while moving data one stage through the instruction shift register. 14.1.13 Exit1-IR A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-IR state. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. 14.1.14 Pause-IR Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK puts the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is LOW during a rising edge on JTCLK. 14.1.15 Exit2-IR A rising edge on JTCLK with JTMS LOW puts the controller in the Update-IR state. The controller loops back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state. 14.1.16 Update-IR The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW puts the controller in the Run-Test-Idle state. With JTMS HIGH, the controller enters the Select-DR-Scan state. 280 of 286 DS26518 8-Port T1/E1/J1 Transceiver Figure 14-2. TAP Controller State Diagram Test Logic Reset 0 Run Test/ Idle 1 Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 1 0 Exit2 DR 1 Update DR 1 0 0 0 1 0 1 1 Select IR-Scan 0 Capture IR 0 Shift IR 1 Exit IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 1 0 1 1 0 281 of 286 DS26518 8-Port T1/E1/J1 Transceiver 14.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH moves the controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS26518 and its respective operational binary codes are shown in Table 14-1. Table 14-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SAMPLE:PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001 14.2.1 SAMPLE:PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be sampled at the Boundary Scan Register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE:PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the Shift-DR state. 14.2.2 BYPASS When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the one-bit Bypass Test Register. This allows data to pass from JTDI to JTDO without affecting the device's normal operation. 14.2.3 EXTEST This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The Boundary Scan Register will be connected between JTDI and JTDO. The Capture-DR will sample all digital inputs into the Boundary Scan Register. 14.2.4 CLAMP All digital outputs of the device will output data from the boundary scan parallel output while connecting the Bypass Register between JTDI and JTDO. The outputs will not change during the CLAMP instruction. 14.2.5 HIGHZ All digital outputs of the device will be placed in a high-impedance state. The Bypass Register will be connected between JTDI and JTDO. 14.2.6 IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code will always have a "1" in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. 282 of 286 DS26518 8-Port T1/E1/J1 Transceiver 14.3 JTAG ID Codes Table 14-2. ID Code Structure DEVICE DS26519 DS26518 REVISION ID[31:28] Consult factory Consult factory DEVICE CODE ID[27:12] 0000000010001011 0000000010001010 MANUFACTURER'S CODE ID[11:1] 00010100001 00010100001 REQUIRED ID[0] 1 1 14.4 Test Registers IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An optional test register, the Identification Register, has been included with the DS26518 design. The Identification Register is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. 14.4.1 Boundary Scan Register This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells, and is n bits in length. 14.4.2 Bypass Register This register is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, providing a short path between JTDI and JTDO. 14.4.3 Identification Register The Identification Register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. 283 of 286 DS26518 8-Port T1/E1/J1 Transceiver 15. 15.1 A B C D E F G H J K L M N P R T PIN CONFIGURATION Pin Configuration--256-Ball TE-CSBGA 1 TTIP1 2 TTIP1 3 TRING1 4 RSYNC1 5 TCHBLK1/ TCHCLK1 6 TSIG2 7 REFCLKIO 8 A11 9 A7 10 A1 11 TSIG7 12 RSIG7 13 TSYNC8/ TSSYNCIO8 14 TRING8 15 TTIP8 16 TTIP8 A B C D E F G H J K L M N P R T ATVDD ATVSS TRING1 TSYNC1/ RCHBLK2/ TSSYNCIO1 RCHCLK2 RSYNC2 MCLK A10 A8 A2 TSYNC7/ TSSYNCIO7 RSER7 TCLK8 TRING8 ATVSS ATVDD RTIP1 RRING1 SPI_SEL/ RMSYNC1/ AL/RSIGF/ RFSYNC1 FLOS1 CLKO/ RLF/LTC1 TCLK1 RMSYNC2/ TCHBLK2/ RFSYNC2 TCHCLK2 A12 A6 A0 RSYNC7 RCHBLK7/ RCHCLK7 TSIG8 TSYSCLK8/ AL/RSIGF/ FLOS8 RSYSCLK8/ RLF/LTC8 RRING8 RTIP8 ARVDD ARVSS RSIG1 TSIG1 RSER2 TCLK2 DIGIOEN A5 TCHBLK7/ RMSYNC7/ TCHCLK7 RFSYNC7 TSER8 RSYNC8 ARVSS ARVDD ARVDD ARVSS RSYSCLK2/ RCHBLK1/ RLF/LTC2 RCHCLK1 TSYSCLK2/ AL/RSIGF/ FLOS2 RSER1 RSIG2 TSER2 BPCLK1 A4 TCLK7 TCHBLK8/ RMSYNC8/ TCHCLK8 RFSYNC8 RCLK8 RSYSCLK7/ RLF/LTC7 TSYSCLK7/ AL/RSIGF/ FLOS7 ARVSS ARVDD RTIP2 RRING2 RCLK1 JTCLK TSER1 TSYNC2/ TSSYNCIO2 A9 A3 TSER7 RSER8 RSIG8 RCLK7 RRING7 RTIP7 ATVDD ATVSS TRING2 RCLK2 DVDD33 DVDD33 DVDD18 DVDD18 DVDD18 DVDD18 DVDD33 DVDD33 RCHBLK8/ RCHCLK8 TRING7 ATVSS ATVDD TTIP2 TTIP2 TRING2 JTDI DVDD33 DVDD33 ACVDD DVDD33 DVDD33 DVDD33 DVDD33 DVSS SCANMODE TRING7 TTIP7 TTIP7 TTIP3 TTIP3 TRING3 JTDO RESREF DVSS ACVSS DVSS DVSS DVSS DVSS RESETB RCLK6 TRING6 TTIP6 TTIP6 ATVDD ATVSS TRING3 JTMS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS RCLK5 TRING6 ATVSS ATVDD RTIP3 RRING3 TSYSCLK3/ AL/RSIGF/ FLOS3 RSYSCLK3/ RLF/LTC3 RCLK3 JTRST RCHBLK3/ TCHBLK3/ RCHCLK3 TCHCLK3 TCLK4 D[1]/ SPI_MOSI TCLK5 TSER6 RSYSCLK1 TSYSCLK6/ TXENABLE/ AL/RSIGF/ SCAN_EN FLOS6 RSYSCLK6/ RLF/LTC6 RRING6 RTIP6 ARVDD ARVSS RCLK4 RSIG3 TSYNC3/ TSYNC4/ TSSYNCIO3 TSSYNCIO4 RDB/ DSB D[5]/ SPI_SWAP TSER5 RSER5 RSER6 BTS ARVSS ARVDD ARVDD ARVSS RSYSCLK4/ RLF/LTC4 RSER3 RSYNC3 RSER4 TSER4 D[0]/ D[6]/ TSYNC5/ SPI_MISO SPI_CPHA TSSYNCIO5 TCLK6 RMSYNC6/ RSYSCLK5/ TSSYNCIO RFSYNC6 RLF/LTC5 TSYSCLK5/ TSYSCLK1 AL/RSIGF/ FLOS5 ARVSS ARVDD RTIP4 RRING4 TSYSCLK4/ RMSYNC3/ AL/RSIGF/ RFSYNC3 FLOS4 TCLK3 RMSYNC4/ TCHBLK4/ RFSYNC4 TCHCLK4 D[2]/ SPI_SCLK TCHBLK5/ RMSYNC5/ TCHBLK6/ TCHCLK5 RFSYNC5 TCHCLK6 RSYNC6 RRING5 RTIP5 ATVDD ATVSS TRING4 TSER3 RSIG4 TSIG4 WRB/ RWB D[4] INTB RSYNC5 RSIG5 TSIG6 RSIG6 TRING5 ATVSS ATVDD TTIP4 TTIP4 TRING4 TSIG3 RSYSCLK/ CLK4 RSYNC4 CSB D[3] D[7]/ SPI_CPOL TSIG5 RCHBLK5/ TSYNC6/ RCHBLK6/ RCHCLK5 TSSYNCIO6 RCHCLK6 TRING5 TTIP5 TTIP5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 284 of 286 DS26518 8-Port T1/E1/J1 Transceiver 16. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 16.1 256-Ball TE-CSBGA (56-G6028-001) 285 of 286 DS26518 8-Port T1/E1/J1 Transceiver 17. DOCUMENT REVISION HISTORY DESCRIPTION New Product Release. 022007 REVISION 286 of 286 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. |
Price & Availability of DS26518G
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |